Journal: IEEE Micro

Volume 20, Issue 6

0 -- 0. New Products
2 -- 3. Micro News
4 -- 0Richard H. Stern. Napster: A Walking Copyright Infringement?
6 -- 7Shane M. Greenstein. PCs, the Internet, and You
8 -- 9Gary S. Robinson. Making Standards Simple
10 -- 11Ken Sakamura. Guest Editor s Introduction: Stepping Into the Future
12 -- 25Marc Tremblay, Jeffrey Chan, Shailender Chaudhry, Andrew W. Conigliaro, Shing Sheung Tse. The MAJC Architecture: A Synthesis of Parallelism and Scalability
26 -- 44David Brooks, Pradip Bose, Stanley Schuster, Hans M. Jacobson, Prabhakar Kudva, Alper Buyuktosunoglu, John-David Wellman, Victor V. Zyuban, Manish Gupta, Peter W. Cook. Power-Aware Microarchitecture: Design and Modeling Challenges for Next-Generation Microprocessors
52 -- 59Gene Frantz. Digital Signal Processor Trends
60 -- 68Rakesh Krishnaiyer, Dattatraya Kulkarni, Daniel M. Lavery, Wei Li, Chu-Cheow Lim, John Ng, David C. Sehr. An Advanced Optimizer for the IA-64 Architecture
69 -- 75Eric Dahlen, Jennifer Gustin, Susan Meredith, Doug Moran. The 82460GX Sever/Workstation Chip Set
76 -- 82Humayun Khalid. Validating Trace-Driven Microarchitectural Simulations
83 -- 84Tadao Nakamura. Cool Chips III
96 -- 0. Product Summary

Volume 20, Issue 5

2 -- 0Ken Sakamura. Connecting Will Be Commonplace
3 -- 0. Micro News
5 -- 6Richard Mateosian. Interaction Design
7 -- 0Shane M. Greenstein. Falling Through the Cracks at Microsoft
9 -- 11John Crawford. Guest Editor s Introduction: Introducing the Itanium Processors
12 -- 23Jerome C. Huck, Dale Morris, Jonathan Ross, Allan D. Knies, Hans Mulder, Rumi Zahir. Introducing the IA-64 Architecture
24 -- 43Harsh Sharangpani, Ken Arora. Itanium Processor Microarchitecture
44 -- 53Jay Bharadwaj, William Y. Chen, Weihaw Chuang, Gerolf Hoflehner, Kishore N. Menezes, Kalyan Muthukumar, Jim Pierce. The Intel IA-64 Compiler Code Generator
54 -- 60Fumio Aono, Masayuki Kimura. The AzusA 16-Way Itanium Server
61 -- 69Nhon T. Quach. High Availability and Reliability in the Itanium Processor
70 -- 83Dezsö Sima. The Design Space of Register Renaming Techniques
84 -- 0Gary S. Robinson. Formal SDOs: They re Still Alive
88 -- 0. Product Summary

Volume 20, Issue 4

5 -- 6Shane M. Greenstein. Hung up on AT&T
7 -- 0Richard Mateosian. Summer Cleanup
10 -- 11Ken Sakamura. 21st-Century Microprocessors
12 -- 20Masato Edahiro, Satoshi Matsushita, Masakazu Yamashina, Naoki Nishi. A Single-Chip Multiprocessor for Smart Terminals
21 -- 27Atsuhiro Suga, Kunihiko Matsunami. Introducing the FR500 Embedded Microprocessor
28 -- 39Prasenjit Biswas, Atsushi Hasegawa, Srinivas Mandaville, Mark Debbage, Andy Sturges, Fumio Arakawa, Yasuhiko Saito, Kunio Uchiyama. SH-5: The 64-Bit SuperH Architecture
40 -- 46Shigeo Araki. The Memory Stick
47 -- 57Srinivas K. Raman, Vladimir M. Pentkovski, Jagannath Keshava. Implementing Streaming SIMD Extensions on the Pentium III Processor
58 -- 66F. Jesús Sánchez, Antonio González. Analyzing Data Locality in Numeric Applications
67 -- 75Michael J. Flynn, Patrick Hung, Armita Peymandoust. Using Simple Tools to Evaluate Complex Architectural Trade-offs
76 -- 84Silke Draber. Optimizing Fault Tolerance in Embedded Distributed Systems

Volume 20, Issue 3

0 -- 87. News
2 -- 0Ken Sakamura. Developing New Computer Architectures
4 -- 5Richard Mateosian. Doing it right
6 -- 7Richard H. Stern. IP-related Refusals to Deal: Part 2 1/2: A Postscript
8 -- 9Shane M. Greenstein. Living in the Era of Impatience
10 -- 12Alan Clements. Guest Editor s Introduction: Computer Architecture Education
13 -- 22Alan Clements. The Undergraduate Curriculum in Computer Architecture
23 -- 28Daniel C. Hyde. Teaching Design in a Computer Architecture Course
29 -- 37James O. Hamblen. Rapid Prototyping Using Field-Programmable Logic Devices
38 -- 47Nirav H. Kapadia, Renato J. O. Figueiredo, José A. B. Fortes. PUNCH: Web Portal for Running Tools
48 -- 56Augustus K. Uht, Jien-Chung Lo, Ying Sun, James C. Daly, James Kowalski. Building Real Computer Systems
57 -- 65Roland N. Ibbett. HASE DLX Simulation Model
66 -- 74Jovan Djordjevic, Aleksandar Milenkovic, Nenad Grbanovic. An Integrated Environment for Teaching Computer Architecture
75 -- 84Arvind, Anton T. Dahbura, Alejandro Caro. From Monsoon to StarT-Voyager: University-Industry Collaboration
85 -- 86Gary S. Robinson. Join a Standards Group and See the World
88 -- 0. Product Summary

Volume 20, Issue 2

0 -- 0. Product Summary
2 -- 0Ken Sakamura. New Applications and Demands
3 -- 4Gary S. Robinson. The Good, the Bad, and the Ugly
4 -- 0. Letters
5 -- 7Shane M. Greenstein. A Revolution? How Do You Know?
8 -- 11Richard H. Stern. IP-Related Refusals to Deal-Part 2: Pretext and Misconduct as Standards
12 -- 0Richard Mateosian. Windows 2000
14 -- 15Monica S. Lam, Forest Baskett. Guest Editors Introduction: Cutting-Edge Designs
16 -- 26Henry Samueli. The Broadband Revolution
27 -- 38Edward H. Frank, Jack Holloway. Connecting the Home With a Phone Line Network Chip Set
40 -- 47Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki. Vector Unit Architecture for Emotion Synthesis
48 -- 59Chris Basoglu, Woobin Lee, John Setel O Donnell. The MAP1000A VLIW Mediaprocessor
60 -- 70Ricardo E. Gonzalez. Xtensa: A Configurable and Extensible Processor
71 -- 84Lance Hammond, Benedict A. Hubbert, Michael Siu, Manohar K. Prabhu, Michael K. Chen, Kunle Olukotun. The Stanford Hydra CMP
85 -- 95Keith Diefendorff, Pradeep K. Dubey, Ron Hochsprung, Hunter Scales. AltiVec Extension to PowerPC Accelerates Media Processing

Volume 20, Issue 1

2 -- 3Ken Sakamura. Performance in the New Millennium
3 -- 0. Letters
4 -- 5. Micro News
6 -- 8Gary S. Robinson. Standards Intellectual Property Licensing
9 -- 0Richard H. Stern. IP-Related Refusals to Deal. Part 1: Updating the Intel-Intergraph Controversy
13 -- 14Shane M. Greenstein. Aggressive Business Tactics: Are There Limits?
15 -- 17Anujan Varma, Mark Laubach. Guest Editors Introduction: Solving Interconnection Problems
18 -- 26Charles D. Cranor, R. Gopalakrishnan, Peter Z. Onufryk. Architectural Considerations for CPU and Network Interface Integration
28 -- 33Tzi-cker Chiueh, Prashant Pradhan. Cache Memory Design for Internet Processors
34 -- 41Pankaj Gupta, Nick McKeown. Classifying Packets with Hierarchical Intelligent Cuttings
42 -- 48L. Louis Zhang, Brent Beacham, Massoud R. Hashemi, Paul Chow, Alberto Leon-Garcia. A Scheduler ASIC for a Programmable Packet Switch
49 -- 57Benjamin Reed, Edward G. Chron, Randal C. Burns, Darrell D. E. Long. Authenticating Network-Attached Storage
58 -- 65Dan Steinberg, Yitzhak Birk. An Empirical Analysis of the IEEE-1394 Serial Bus Protocol
66 -- 76José Fridman, Zvi Greenfield. The TigerSHARC DSP Architecture
77 -- 78Richard Mateosian. Happy New Year
79 -- 80Stephen L. Diamond. Microdisplay Applications Reach the Mainstream