| 743 | -- | 755 | Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske. Using simulation and satisfiability to compute flexibilities in Boolean networks |
| 756 | -- | 771 | Girish Venkataramani, Tobias Bjerregaard, Tiberiu Chelcea, Seth Copen Goldstein. Hardware compilation of application-specific memory-access interconnect |
| 772 | -- | 779 | Philip Brisk, Foad Dabiri, Roozbeh Jafari, Majid Sarrafzadeh. Optimal register sharing for high-level synthesis of SSA form programs |
| 780 | -- | 788 | Subramanian K. Iyer, Debashis Sahoo, E. Allen Emerson, Jawahar Jain. On partitioning and symbolic model checking |
| 789 | -- | 796 | Tsutomu Sasao. Analysis and synthesis of weighted-sum functions |
| 797 | -- | 805 | Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias. Comparison of two designs for the multifunction vehicle bus |
| 806 | -- | 820 | Ying Yi, Roger Woods. Hierarchical synthesis of complex DSP functions using IRIS |
| 821 | -- | 836 | Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James Tschanz, Vivek De. Formal derivation of optimal active shielding for low-power on-chip buses |
| 837 | -- | 855 | Srinivas Bodapati, Farid N. Najm. High-level current macro model for logic blocks |
| 856 | -- | 866 | Yan Feng, Dinesh P. Mehta. Module relocation to obtain feasible constrained floorplans |
| 867 | -- | 877 | Premachandran R. Menon, Weifeng Xu, Russell Tessier. Design-specific path delay testing in lookup-table-based FPGAs |
| 878 | -- | 891 | Haralampos-G. D. Stratigopoulos, Yiorgos Makris. Concurrent detection of erroneous responses in linear analog circuits |
| 892 | -- | 901 | Kanak Agarwal, Dennis Sylvester, David Blaauw. Modeling and analysis of crosstalk noise in coupled RLC interconnects |
| 902 | -- | 909 | Rüdiger Ebendt, Rolf Drechsler. Effect of improved lower bounds in dynamic BDD reordering |
| 909 | -- | 913 | Kooho Jung, William R. Eisenstadt, Robert M. Fox. SPICE-based mixed-mode S-parameter calculations for four-port and three-port circuits |
| 913 | -- | 917 | Hong Sik Kim, Sungho Kang. Increasing encoding efficiency of LFSR reseeding-based test compression |
| 917 | -- | 924 | Xun Liu, Yuantao Peng, Marios C. Papaefthymiou. Practical repeater insertion for low power: what repeater library do we need? |
| 924 | -- | 932 | Ewout Martens, Georges G. E. Gielen. Analyzing continuous-time Delta-Sigma-Modulators with generic behavioral models |
| 932 | -- | 938 | Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram. An error control method for application of the discrete cosine transform to extraction of substrate parasitics in ICs |