| 409 | -- | 422 | Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh. Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration |
| 423 | -- | 435 | Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown. Scalable Synthesis and Clustering Techniques Using Decision Diagrams |
| 436 | -- | 444 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne. Quantum Circuit Simplification and Level Compaction |
| 445 | -- | 455 | Sarvesh Bhardwaj, Sarma B. K. Vrudhula. Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations |
| 456 | -- | 469 | Kin Cheong Sou, Alexandre Megretski, Luca Daniel. A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction |
| 470 | -- | 480 | Ngai Wong. Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations |
| 481 | -- | 494 | Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw. Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias |
| 495 | -- | 507 | Baolin Yang, Yu Zhu, Ali Bouaricha, Joel R. Phillips. Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation |
| 508 | -- | 515 | Peter Hallschmid, Resve Saleh. Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs |
| 516 | -- | 527 | Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long. Optimizing Thermal Sensor Allocation for Microprocessors |
| 528 | -- | 541 | Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk. CHIPS: Custom Hardware Instruction Processor Synthesis |
| 542 | -- | 555 | Hristo Nikolov, Todor Stefanov, Ed F. Deprettere. Systematic and Automated Multiprocessor System Design, Programming, and Implementation |
| 556 | -- | 569 | Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar. An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis |
| 570 | -- | 574 | Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda. An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores |
| 574 | -- | 578 | Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub. A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform |
| 578 | -- | 583 | Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim. A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm |
| 583 | -- | 587 | Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy. On Complete Functional Broadside Tests for Transition Faults |