External Links

    Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

    Volume 27, Issue 9

    1521 -- 1534Igor Vytyaz, David C. Lee, Pavan Kumar Hanumolu, Un-Ku Moon, Kartikeya Mayaram. Sensitivity Analysis for Oscillators
    1535 -- 1544Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi. A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models
    1545 -- 1554Y.-J. J. Yang, C.-W. Kuo. Generating Scalable and Modular Macromodels for Microchannels Using the Galerkin-Based Technique
    1555 -- 1564Hassan Hassan, Mohab Anis, Mohamed I. Elmasry. Input Vector Reordering for Leakage Power Reduction in FPGAs
    1565 -- 1570Aijiao Cui, Chip-Hong Chang, Sofiène Tahar. IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level
    1571 -- 1582Yung-Ta Li, Zhaojun Bai, Yangfeng Su, Xuan Zeng. Model Order Reduction of Parameterized Interconnect Networks via a Two-Directional Arnoldi Process
    1583 -- 1594Hiran Tennakoon, Carl Sechen. Nonconvex Gate Delay Modeling and Delay Optimization
    1595 -- 1606Chenggang Xu, Ranjit Gharpurey, Terri S. Fiez, Kartikeya Mayaram. Extraction of Parasitics in Inhomogeneous Substrates With a New Green Function-Based Method
    1607 -- 1620Ulrich Brenner, Markus Struzyna, Jens Vygen. BonnPlace: Placement of Leading-Edge Chips by Advanced Combinatorial Algorithms
    1621 -- 1634Tung-Chieh Chen, Ping-Hung Yuh, Yao-Wen Chang, Few-Juh Huang, T.-Y. Liu. MP-Trees: A Packing-Based Macro Placement Algorithm for Modern Mixed-Size Designs
    1635 -- 1642Andrew B. Kahng, Chul-Hong Park, Xu Xu. Fast Dual-Graph-Based Hotspot Filtering
    1643 -- 1656T. H. Lee, T.-C. Wang. Congestion-Constrained Layer Assignment for Via Minimization in Global Routing
    1657 -- 1669Munkang Choi, Linda S. Milor. Diagnosis of Optical Lithography Faults With Product Test Sets
    1670 -- 1683Fu-Ching Yang, Wen-Kai Huang, Jing-Kun Zhong, Ing-Jer Huang. Automatic Verification of External Interrupt Behaviors for Microprocessor Design
    1684 -- 1688J.-C. Guo, Y. M. Lin. A Compact RF CMOS Modeling for Accurate High-Frequency Noise Simulation in Sub-100-nm MOSFETs
    1689 -- 1692Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan. Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs
    1693 -- 1697H.-C. Liang, P.-H. Huang, Y.-F. Tang. Testing Transition Delay Faults in Modified Booth Multipliers

    Volume 27, Issue 8

    1349 -- 1362Jason Cong, Min Xie. A Robust Mixed-Size Legalization and Detailed Placement Algorithm
    1363 -- 1375. An Efficient Graph-Based Algorithm for ESD Current Path Analysis
    1376 -- 1384Maharaj Mukherjee, Kanad Chakraborty. A Randomized Greedy Method for Rectangular-Pattern Fill Problems
    1385 -- 1397Uday Padmanabhan, Janet Meiling Wang, Jiang Hu. Robust Clock Tree Routing in the Presence of Process Variations
    1398 -- 1411Peter Spindler, Ulf Schlichtmann, Frank M. Johannes. Kraftwerk2 - A Fast Force-Directed Quadratic Placement Approach Using an Accurate Net Model
    1412 -- 1424Giovanni Agosta, Francesco Bruschi, Donatella Sciuto. Static Analysis of Transaction-Level Communication Models
    1425 -- 1438Karam S. Chatha, Krishnan Srinivasan, Goran Konjevod. Automated Techniques for Synthesis of Application-Specific Network-on-Chip Architectures
    1439 -- 1452Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil D. Dutt. Data-Reuse-Driven Energy-Aware Cosynthesis of Scratch Pad Memory and Hierarchical Bus-Based Communication Architecture for Multiprocessor Streaming Applications
    1453 -- 1466Ozgur Sinanoglu, Tsvetomir Petrov. Isolation Techniques for Soft Cores
    1467 -- 1478Changjiu Xian, Yung-Hsiang Lu, Zhiyuan Li. Dynamic Voltage Scaling for Multitasking Real-Time Systems With Uncertain Execution Time
    1479 -- 1492Changyun Zhu, Zhenyu (Peter) Gu, Li Shang, Robert P. Dick, Russ Joseph. Three-Dimensional Chip-Multiprocessor Run-Time Thermal Management
    1493 -- 1497Soumya Pandit, Sumit K. Bhattacharya, Chittaranjan A. Mandal, Amit Patra. A Fast Exploration Procedure for Analog High-Level Specification Translation
    1498 -- 1502King Ho Tam, Yu Hu, Lei He, Tom Tong Jing, Xinyi Zhang. Dual-V::dd:: Buffer Insertion for Power Reduction
    1503 -- 1507Shuai Wang, Jie Hu, Sotirios G. Ziavras. Self-Adaptive Data Caches for Soft-Error Reliability
    1508 -- 1513Wenjian Yu, Xiren Wang, Zuochang Ye, Zeyi Wang. Efficient Extraction of Frequency-Dependent Substrate Parasitics Using Direct Boundary Element Method
    1513 -- 1517Aleksandr Zaks, Zijiang Yang, Ilya Shlyakhter, Franjo Ivancic, Srihari Cadambi, Malay K. Ganai, Aarti Gupta, Pranav Ashar. Bitwidth Reduction via Symbolic Interval Analysis for Software Model Checking

    Volume 27, Issue 7

    1165 -- 1178Vijay D Silva, Daniel Kroening, Georg Weissenbacher. A Survey of Automated Techniques for Formal Software Verification
    1179 -- 1189R. Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández. An Integrated Layout-Synthesis Approach for Analog ICs
    1190 -- 1202Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa. Logic Minimization and Testability of 2-SPP Networks
    1203 -- 1213Lei Cheng, Deming Chen, Martin D. F. Wong. DDBDD: Delay-Driven BDD Synthesis for FPGAs
    1214 -- 1227Taehoon Kim, Yungseon Eo. Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines
    1228 -- 1240Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints
    1241 -- 1252Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu. Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
    1253 -- 1263Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He. Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
    1264 -- 1277Soner Yaldiz, Alper Demir, Serdar Tasiran. Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study
    1278 -- 1290Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer. Low-Power Test Data Application in EDT Environment Through Decompressor Freeze
    1291 -- 1304Sari Onaissi, Farid N. Najm. A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
    1305 -- 1314Daniel Große, Ulrich Kühne, Rolf Drechsler. Analyzing Functional Coverage in Bounded Model Checking
    1315 -- 1328Xiaoxi Xu, Cheng-Chew Lim. Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip
    1329 -- 1333Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille. On Acceleration of SAT-Based ATPG for Industrial Designs
    1333 -- 1338Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos. Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
    1338 -- 1343Jing-ling Yang, Qiang Xu. State-Sensitive X-Filling Scheme for Scan Capture Power Reduction
    1343 -- 1347Hao Zheng, Jared Ahrens, Tian Xia. A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification

    Volume 27, Issue 6

    985 -- 998Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang. Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis
    999 -- 1012Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara. A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST
    1013 -- 1026Levent Aksoy, Eduardo da Costa, Paulo F. Flores, José Monteiro. Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications
    1027 -- 1040Javid Jaffari, Mohab Anis. Statistical Thermal Profile Considering Process Variations: Analysis and Applications
    1041 -- 1054Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi. Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations
    1055 -- 1065Zhe-Wei Jiang, Yao-Wen Chang. An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing
    1066 -- 1077Jarrod A. Roy, Igor L. Markov. High-Performance Routing at the Nanometer Scale
    1078 -- 1090Pramod Chandraiah, Rainer Dömer. Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding
    1091 -- 1103Tarvo Raudvere, Ingo Sander, Axel Jantsch. Application and Verification of Local Nonsemantic-Preserving Transformations in System Design
    1104 -- 1116Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li. Diagnosis of Multiple Scan Chain Timing Faults
    1117 -- 1127S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod. Bridging Fault Test Method With Adaptive Power Management Awareness
    1128 -- 1137Afshin Abdollahi, Massoud Pedram. Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions
    1138 -- 1149Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler. Automatic Fault Localization for Property Checking
    1150 -- 1154Brajesh Kumar Kaushik, Sankar Sarkar. Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects
    1155 -- 1159Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie. Register File Power Reduction Using Bypass Sensitive Compiler
    1159 -- 1164Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli. An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting

    Volume 27, Issue 5

    781 -- 790Paolo Maffezzoni. Unified Computation of Parameter Sensitivity and Signal-Injection Sensitivity in Nonlinear Oscillators
    791 -- 802Lihong Zhang, Nuttorn Jangkrajarng, Sambuddha Bhattacharya, C.-J. Richard Shi. Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach
    803 -- 816Natasa Miskov-Zivanov, Diana Marculescu. Modeling and Optimization for Soft-Error Reliability of Sequential Circuits
    817 -- 830S. Srivastava, J. Roychowdhury. Independent and Interdependent Latch Setup/Hold Time Characterization via Newton-Raphson Solution and Euler Curve Tracking of State-Transition Equations
    831 -- 843Xin Li, Yaping Zhan, Lawrence T. Pileggi. Quadratic Statistical MAX Approximation for Parametric Yield Estimation of Analog/RF Integrated Circuits
    844 -- 857Huang-Yu Chen, Mei-Fang Chiang, Yao-Wen Chang, Lumdo Chen, Brian Han. Full-Chip Routing Considering Double-Via Insertion
    858 -- 871Song Chen, Takeshi Yoshimura. Fixed-Outline Floorplanning: Block-Position Enumeration and a New Method for Calculating Area Costs
    872 -- 882Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan. Track Routing and Optimization for Yield
    883 -- 892Bo Hu, C.-J. Richard Shi. Simulation of Closely Related Dynamic Nonlinear Systems With Application to Process-Voltage-Temperature Corner Analysis
    893 -- 905Diana Marculescu, Siddharth Garg. Process-Driven Variability Analysis of Single and Multiple Voltage-Frequency Island Latency-Constrained Systems
    906 -- 919Claudio Pinello, Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli. Fault-Tolerant Distributed Deployment of Embedded Control Software
    920 -- 931Erkan Acar, Sule Ozev. Defect-Oriented Testing of RF Circuits
    932 -- 945Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski. Improving the Resolution of Single-Delay-Fault Diagnosis
    946 -- 957Irith Pomeranz, Sudhakar M. Reddy. On the Saturation of n-Detection Test Generation by Different Definitions With Increased n
    958 -- 962Jeong-Ho Han, In-Cheol Park. FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient
    963 -- 967Xiaojun Ma, Fabrizio Lombardi. Synthesis of Tile Sets for DNA Self-Assembly
    967 -- 972Bhaskar Pal, Ansuman Banerjee, Arnab Sinha, Pallab Dasgupta. Accelerating Assertion Coverage With Adaptive Testbenches
    973 -- 977Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng. Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling
    977 -- 982Gülin Tulunay, Sina Balkir. A Synthesis Tool for CMOS RF Low-Noise Amplifiers

    Volume 27, Issue 4

    589 -- 607David Blaauw, Kaviraj Chopra, Ashish Srivastava, Louis Scheffer. Statistical Timing Analysis: From Basic Principles to State of the Art
    608 -- 609Patrick H. Madden, David Z. Pan. Guest Editorial
    610 -- 620Vishal Khandelwal, Ankur Srivastava. Variability-Driven Formulation for Simultaneous Gate Sizing and Postsilicon Tunability Allocation
    621 -- 632Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong. Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm
    633 -- 642Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong. Fast Dummy-Fill Density Analysis With Coupling Constraints
    643 -- 653Chung-Wei Lin, Szu-Yu Chen, Chi-Feng Li, Yao-Wen Chang, Chia-Lin Yang. Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
    654 -- 658Tung-Chieh Chen, Yi-Lin Chuang, Yao-Wen Chang. Effective Wire Models for X-Architecture Placement
    659 -- 672Cheoljoo Jeong, Steven M. Nowick. Technology Mapping and Cell Merger for Asynchronous Threshold Networks
    673 -- 685Seok-Won Seong, Prabhat Mishra. Bitmask-Based Code Compression for Embedded Systems
    686 -- 697Ryan Fung, Vaughn Betz, William Chow. Slack Allocation and Routing to Improve FPGA Timing While Repairing Short-Path Violations
    698 -- 711Abusaleh M. Jabir, Dhiraj K. Pradhan, Jimson Mathew. GfXpress: A Technique for Synthesis and Optimization of GF(2:::m:::) Polynomials
    712 -- 725Ying Wei, Alex Doboli. Structural Macromodeling of Analog Circuits Through Model Decoupling and Transformation
    726 -- 737Zhen Cao, Tong Jing, Jinjun Xiong, Yu Hu, Zhe Feng 0002, Lei He, Xianlong Hong. Fashion: A Fast and Accurate Solution to Global Routing Problem
    738 -- 751Cheng Zhuo, Jiang Hu, Min Zhao, Kangsheng Chen. Power Grid Analysis and Optimization Using Algebraic Multigrid
    752 -- 763Dmitri Maslov, Sean M. Falconer, Michele Mosca. Quantum Circuit Placement
    764 -- 777Neil Kettle, Andy King. An Anytime Algorithm for Generalized Symmetry Detection in ROBDDs

    Volume 27, Issue 3

    409 -- 422Sejong Oh, Tag Gon Kim, Jeonghun Cho, Elaheh Bozorgzadeh. Speculative Loop-Pipelining in Binary Translation for Hardware Acceleration
    423 -- 435Andrew C. Ling, Jianwen Zhu, Stephen Dean Brown. Scalable Synthesis and Clustering Techniques Using Decision Diagrams
    436 -- 444Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller, C. Negrevergne. Quantum Circuit Simplification and Level Compaction
    445 -- 455Sarvesh Bhardwaj, Sarma B. K. Vrudhula. Leakage Minimization of Digital Circuits Using Gate Sizing in the Presence of Process Variations
    456 -- 469Kin Cheong Sou, Alexandre Megretski, Luca Daniel. A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction
    470 -- 480Ngai Wong. Efficient Positive-Real Balanced Truncation of Symmetric Systems Via Cross-Riccati Equations
    481 -- 494Sarvesh H. Kulkarni, D. M. Sylvester, David T. Blaauw. Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias
    495 -- 507Baolin Yang, Yu Zhu, Ali Bouaricha, Joel R. Phillips. Applications of the Multi-Interval Chebyshev Collocation Method in RF Circuit Simulation
    508 -- 515Peter Hallschmid, Resve Saleh. Fast Design Space Exploration Using Local Regression Modeling With Application to ASIPs
    516 -- 527Seda Ogrenci Memik, Rajarshi Mukherjee, Min Ni, Jieyi Long. Optimizing Thermal Sensor Allocation for Microprocessors
    528 -- 541Kubilay Atasu, Can C. Özturan, Günhan Dündar, Oskar Mencer, Wayne Luk. CHIPS: Custom Hardware Instruction Processor Synthesis
    542 -- 555Hristo Nikolov, Todor Stefanov, Ed F. Deprettere. Systematic and Automated Multiprocessor System Design, Programming, and Implementation
    556 -- 569Chandan Karfa, Dipankar Sarkar, Chitta Mandal, P. Kumar. An Equivalence-Checking Method for Scheduling Verification in High-Level Synthesis
    570 -- 574Paolo Bernardi, Ernesto Sánchez, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda. An Effective Technique for the Automatic Generation of Diagnosis-Oriented Programs for Processor Cores
    574 -- 578Changzhong Chen, Dharmendra Saraswat, Ramachandra Achar, Emad Gad, Michel S. Nakhla, Mustapha Chérif-Eddine Yagoub. A Robust Algorithm for Passive Reduced-Order Macromodeling of MTLs With FD-PUL Parameters Using Integrated Congruence Transform
    578 -- 583Chaeho Chung, Soobum Lee, Byung Man Kwak, Gawon Kim, Joungho Kim. A Delay Line Circuit Design for Crosstalk Minimization Using Genetic Algorithm
    583 -- 587Hangkyu Lee, Irith Pomeranz, Sudhakar M. Reddy. On Complete Functional Broadside Tests for Transition Faults

    Volume 27, Issue 2

    205 -- 216Javid Jaffari, Mohab Anis. Variability-Aware Bulk-MOS Device Design
    217 -- 229R. Mahesh, A. Prasad Vinod. A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters
    230 -- 240Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma. Defocus-Aware Leakage Estimation and Control
    241 -- 248Ja Chun Ku, Yehea I. Ismail. Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies
    249 -- 264Ning Dong, Jaijeet S. Roychowdhury. General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations
    265 -- 271Alexander Heldring, Juan M. Rius, José Maria Tamayo, Josep Parrón. Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction
    272 -- 285Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw. A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance
    286 -- 294Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin. A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning
    295 -- 308Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar. A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation
    309 -- 326Shantanu Dutt, Vinay Verma, Vishal Suthar. Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing
    327 -- 338Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing
    339 -- 351Haralampos-G. D. Stratigopoulos, Yiorgos Makris. Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing
    352 -- 365Zhanglei Wang, Krishnendu Chakrabarty. Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns
    366 -- 379Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke. Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog
    380 -- 393Ilya Wagner, Valeria Bertacco, Todd M. Austin. Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors
    394 -- 398Hiren D. Patel, Sandeep K. Shukla. On Cosimulating Multiple Abstraction-Level System-Level Models
    398 -- 403Irith Pomeranz, Sudhakar M. Reddy. Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test
    403 -- 407Aleksandra Sesic, Stanisa Dautovic, Veljko Malbasa. Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking

    Volume 27, Issue 12

    2105 -- 2106David Z. Pan, Gi-Joon Nam. Guest Editorial
    2107 -- 2119Stephen Plaza, Igor L. Markov, Valeria Bertacco. Optimizing Nonmonotonic Interconnect Using Functional Simulation and Logic Restructuring
    2120 -- 2132Hosung Kim, John Lillis. A Layout-Level Logic Restructuring Framework for LUT-Based FPGAs
    2133 -- 2144Jason Cong, Guojie Luo, E. Radke. Highly Efficient Gradient Computation for Density-Constrained Analytical Placement
    2145 -- 2155Tung-Chieh Chen, Minsik Cho, David Z. Pan, Yao-Wen Chang. Metal-Density-Driven Placement for CMP Variation and Routability
    2156 -- 2168David A. Papa, Tao Luo, Michael D. Moffitt, Chin-Ngai Sze, Zhuo Li, Gi-Joon Nam, Charles J. Alpert, Igor L. Markov. RUMBLE: An Incremental Timing-Driven Physical-Synthesis Optimization Algorithm
    2169 -- 2182Jieyi Long, Hai Zhou, Seda Ogrenci Memik. EBOARST: An Efficient Edge-Based Obstacle-Avoiding Rectilinear Steiner Tree Construction Algorithm
    2183 -- 2196Yifang Liu, Jiang Hu, Weiping Shi. Buffering Interconnect for Multicore Processor Designs
    2197 -- 2208Kuang-Yao Lee, Cheng-Kok Koh, Ting-Chi Wang, Kai-Yuan Chao. Fast and Optimal Redundant Via Insertion
    2209 -- 2222Tobias Massier, Helmut E. Graeb, Ulf Schlichtmann. The Sizing Rules Method for CMOS and Bipolar Analog Integrated Circuit Synthesis
    2223 -- 2235David Walter, Scott Little, Chris J. Myers, Nicholas Seegmiller, Tomohiro Yoneda. Verification of Analog/Mixed-Signal Circuits Using Symbolic Methods
    2236 -- 2249Tomasz S. Czajkowski, Stephen Dean Brown. Functionally Linear Decomposition and Synthesis of Logic Circuits for FPGAs
    2250 -- 2263Roxana Ionutiu, Joost Rommes, Athanasios C. Antoulas. Passivity-Preserving Model Reduction Using Dominant Spectral-Zero Interpolation
    2264 -- 2276Lin Xie, Azadeh Davoodi. Robust Estimation of Timing Yield With Partial Statistical Information on Process Variations
    2277 -- 2290Rebecca L. Collins, Luca P. Carloni. Topology-Based Performance Analysis and Optimization of Latency-Insensitive Systems
    2291 -- 2302Chunrong Song, Spyros Tragoudas. Identification of Critical Executable Paths at the Architectural Level
    2303 -- 2316Ozgur Sinanoglu. Scan Architecture With Align-Encode
    2317 -- 2330Amith Singhee, Claire Fang Fang, James D. Ma, Rob A. Rutenbar. Probabilistic Interval-Valued Computation: Toward a Practical Surrogate for Statistics Inside CAD Tools

    Volume 27, Issue 11

    1905 -- 1917Tao Xu, Krishnendu Chakrabarty. A Droplet-Manipulation Method for Achieving High-Throughput in Cross-Referencing-Based Digital Microfluidic Biochips
    1918 -- 1927Yang Yi, Peng Li, Vivek Sarin, Weiping Shi. A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics
    1928 -- 1941Ping-Hung Yuh, Chia-Lin Yang, Yao-Wen Chang. BioRoute: A Network-Flow-Based Routing Algorithm for the Synthesis of Digital Microfluidic Biochips
    1942 -- 1955Yung-Chih Chen, Chun-Yao Wang. An Implicit Approach to Minimizing Range-Equivalent Circuits
    1956 -- 1968Jun Seomun, Jae-Hyun Kim, Youngsoo Shin. Skewed Flip-Flop and Mixed-V::t:: Gates for Minimizing Leakage in Sequential Circuits
    1969 -- 1982Yongsoo Joo, Yongseok Choi, Jaehyun Park, Chanik Park, Sung Woo Chung, Eui-Young Chung, Naehyuck Chang. Energy and Performance Optimization of Demand Paging With OneNAND Flash
    1983 -- 1995Mohamed H. Abu-Rahma, Mohab Anis. A Statistical Design-Oriented Delay Variation Model Accounting for Within-Die Variations
    1996 -- 2006Ning Mi, Sheldon X.-D. Tan, Yici Cai, Xianlong Hong. Fast Variational Analysis of On-Chip Power Grids by Stochastic Extended Krylov Subspace Method
    2007 -- 2016Chung-Wei Lin, Shih-Lun Huang, Kai-Chi Hsu, Meng-Xiang Lee, Yao-Wen Chang. Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs
    2017 -- 2026Michael D. Moffitt. MaizeRouter: Engineering an Effective Global Router
    2027 -- 2038Seda Ogrenci Memik, Nikolaos Bellas, Somsubhra Mondal. Presynthesis Area Estimation of Reconfigurable Streaming Accelerators
    2039 -- 2052Seongmoon Wang, Wenlong Wei. An Efficient Unknown BlockingScheme for Low Control Data Volume and High Observability
    2053 -- 2067M. Haykel Ben Jamaa, Kirsten E. Moselund, David Atienza, Didier Bouvet, Adrian M. Ionescu, Yusuf Leblebici, Giovanni De Micheli. Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories
    2068 -- 2082Minh D. Nguyen, Max Thalmaier, Markus Wedler, J. Bormann, Dominik Stoffel, Wolfgang Kunz. Unbounded Protocol Compliance Verification Using Interval Property Checking With Invariants
    2083 -- 2087Sertac Cinel, Cüneyt F. Bazlamaçci. A Distributed Heuristic Algorithm for the Rectilinear Steiner Minimal Tree Problem
    2088 -- 2092Hyunjin Kim, Hyejeong Hong, Hong Sik Kim, Jin-Ho Ahn, Sungho Kang. Total Energy Minimization of Real-Time Tasks in an On-Chip Multiprocessor Using Dynamic Voltage Scaling Efficiency Metric
    2092 -- 2097Ho Fai Ko, Nicola Nicolici. Automated Scan Chain Division for Reducing Shift and Capture Power During Broadside At-Speed Test
    2097 -- 2101Pei-Wen Luo, Jwu-E Chen, Chin-Long Wey, Liang-Chia Cheng, Ji-Jan Chen, Wen Ching Wu. Impact of Capacitance Correlation on Yield Enhancement of Mixed-Signal/Analog Integrated Circuits

    Volume 27, Issue 10

    1701 -- 1713Wayne Wolf, Ahmed Amine Jerraya, Grant Martin. Multiprocessor System-on-Chip (MPSoC) Technology
    1714 -- 1724Minsik Cho, David Z. Pan. A High-Performance Droplet Routing Algorithm for Digital Microfluidic Biochips
    1725 -- 1736Nishant Patil, Jie Deng, Albert Lin, H.-S. Philip Wong, Subhasish Mitra. Design Methods for Misaligned and Mispositioned Carbon-Nanotube Immune Circuits
    1737 -- 1750Alessandro Cimatti, Marco Roveri, Stefano Tonetta. Symbolic Compilation of PSL
    1751 -- 1760Yu Hu, Victor Shih, Rupak Majumdar, Lei He. Exploiting Symmetries to Speed Up SAT-Based Boolean Matching for Logic Synthesis of FPGAs
    1761 -- 1774Ajay K. Verma, Philip Brisk, Paolo Ienne. Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits
    1775 -- 1787Osama Neiroukh, Stephen A. Edwards, Xiaoyu Song. Transforming Cyclic Circuits Into Acyclic Equivalents
    1788 -- 1797Foad Dabiri, Ani Nahapetian, Tammara Massey, Miodrag Potkonjak, Majid Sarrafzadeh. General Methodology for Soft-Error-Aware Power Optimization Using Gate Sizing
    1798 -- 1811Ehsan Pakbaznia, Farzan Fallah, Massoud Pedram. Charge Recycling in Power-Gated CMOS Circuits
    1812 -- 1825Sarvesh Bhardwaj, Sarma B. K. Vrudhula, Amit Goel. A Unified Approach for Full Chip Statistical Timing and Leakage Analysis of Nanoscale Circuits Considering Intradie Process Variations
    1826 -- 1839Khaled R. Heloue, Farid N. Najm. Early Analysis and Budgeting of Margins and Corners Using Two-Sided Analytical Yield Models
    1840 -- 1851Andrew Labun, Karan Jagjitkumar. Rapid Detailed Temperature Estimation for Highly Coupled IC Interconnect
    1852 -- 1865Jin Sun, Jun Li, Dongsheng Ma, Janet Meiling Wang. Chebyshev Affine-Arithmetic-Based Parametric Yield Prediction Under Limited Descriptions of Uncertainty
    1866 -- 1879Chen-Ling Chou, Ümit Y. Ogras, Radu Marculescu. Energy- and Performance-Aware Incremental Mapping for Networks on Chip With Multiple Voltage Levels
    1880 -- 1890Guo Yu, Wei Dong, Zhuo Feng, Peng Li. Statistical Static Timing Analysis Considering Process Variation Model Uncertainty
    1891 -- 1901Kian Haghdad, Mohab Anis. Design-Specific Optimization Considering Supply and Threshold Voltage Variations

    Volume 27, Issue 1

    1 -- 2. Editorial
    3 -- 19Andrew B. Kahng, Kambiz Samadi. CMP Fill Synthesis: A Survey of Recent Studies
    20 -- 33Josep Carmona, Jordi Cortadella. Encoding Large Asynchronous Controllers With ILP Techniques
    34 -- 44Vamsi Vankamamidi, Marco Ottavi, Fabrizio Lombardi. Two-Dimensional Schemes for Clocking/Timing of QCA Circuits
    45 -- 58Shrirang K. Karandikar, Sachin S. Sapatnekar. Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem
    59 -- 69Ting Mei, Jaijeet S. Roychowdhury. A Time-Domain Oscillator Envelope Tracking Algorithm Employing Dual Phase Conditions
    70 -- 83Chris C. N. Chu, Yiu-Chung Wong. FLUTE: Fast Lookup Table Based Rectilinear Steiner Minimal Tree Algorithm for VLSI Design
    84 -- 95Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger. Simultaneous Escape-Routing Algorithms for Via Minimization of High-Speed Boards
    96 -- 108Amit Kumar 0002, Li Shang, Li-Shiuan Peh, Niraj K. Jha. System-Level Dynamic Thermal Management for High-Performance Microprocessors
    109 -- 122Shankar Mahadevan, Federico Angiolini, Jens Sparsø, Luca Benini, Jan Madsen. A Reactive and Cycle-True IP Emulator for MPSoC Exploration
    123 -- 136Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. Experimental Characterization of CMOS Interconnect Open Defects
    137 -- 146Irith Pomeranz, Sudhakar M. Reddy. Unspecified Transition Faults: A Transition Fault Model for At-Speed Fault Simulation and Test Generation
    147 -- 159Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Neelanjan Mukherjee, Mark Kassab. X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector
    160 -- 173Jaskirat Singh, Sachin S. Sapatnekar. A Scalable Statistical Static Timing Analyzer Incorporating Correlated Non-Gaussian and Gaussian Parameter Variations
    174 -- 183Saibal Mukhopadhyay, Hamid Mahmoodi, Kaushik Roy. Reduction of Parametric Failures in Sub-100-nm SRAM Array Using Body Bias
    184 -- 188Kai-Hui Chang, Igor L. Markov, Valeria Bertacco. Fixing Design Errors With Counterexamples and Resynthesis
    188 -- 192Sushanta K. Mandal, Shamik Sural, Amit Patra. ANN- and PSO-Based Synthesis of On-Chip Spiral Inductors for RF ICs
    193 -- 197Irith Pomeranz, Sudhakar M. Reddy. Primary Input Vectors to Avoid in Random Test Sequences for Synchronous Sequential Circuits
    197 -- 201Weixin Wu, Michael S. Hsiao. Mining Global Constraints With Domain Knowledge for Improving Bounded Sequential Equivalence Checking
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