Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 27, Issue 7

1165 -- 1178Vijay D Silva, Daniel Kroening, Georg Weissenbacher. A Survey of Automated Techniques for Formal Software Verification
1179 -- 1189R. Castro-López, Oscar Guerra, Elisenda Roca, Francisco V. Fernández. An Integrated Layout-Synthesis Approach for Analog ICs
1190 -- 1202Anna Bernasconi, Valentina Ciriani, Rolf Drechsler, Tiziano Villa. Logic Minimization and Testability of 2-SPP Networks
1203 -- 1213Lei Cheng, Deming Chen, Martin D. F. Wong. DDBDD: Delay-Driven BDD Synthesis for FPGAs
1214 -- 1227Taehoon Kim, Yungseon Eo. Analytical CAD Models for the Signal Transients and Crosstalk Noise of Inductance-Effect-Prominent Multicoupled RLC Interconnect Lines
1228 -- 1240Tung-Chieh Chen, Zhe-Wei Jiang, Tien-Chang Hsu, Hsin-Chen Chen, Yao-Wen Chang. NTUplace3: An Analytical Placer for Large-Scale Mixed-Size Designs With Preplaced Blocks and Density Constraints
1241 -- 1252Andrew B. Kahng, Puneet Sharma, Rasit Onur Topaloglu. Chip Optimization Through STI-Stress-Aware Placement Perturbations and Fill Insertion
1253 -- 1263Yiyu Shi, Jinjun Xiong, Chunchen Liu, Lei He. Efficient Decoupling Capacitance Budgeting Considering Operation and Process Variations
1264 -- 1277Soner Yaldiz, Alper Demir, Serdar Tasiran. Stochastic Modeling and Optimization for Energy Management in Multicore Systems: A Video Decoding Case Study
1278 -- 1290Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer. Low-Power Test Data Application in EDT Environment Through Decompressor Freeze
1291 -- 1304Sari Onaissi, Farid N. Najm. A Linear-Time Approach for Static Timing Analysis Covering All Process Corners
1305 -- 1314Daniel Große, Ulrich Kühne, Rolf Drechsler. Analyzing Functional Coverage in Bounded Model Checking
1315 -- 1328Xiaoxi Xu, Cheng-Chew Lim. Using Transfer-Resource Graph for Software-Based Verification of System-on-Chip
1329 -- 1333Rolf Drechsler, Stephan Eggersglüß, Görschwin Fey, Andreas Glowatz, Friedrich Hapke, Jürgen Schlöffel, Daniel Tille. On Acceleration of SAT-Based ATPG for Industrial Designs
1333 -- 1338Xrysovalantis Kavousianos, Emmanouil Kalligeros, Dimitris Nikolos. Test Data Compression Based on Variable-to-Variable Huffman Encoding With Codeword Reusability
1338 -- 1343Jing-ling Yang, Qiang Xu. State-Sensitive X-Filling Scheme for Scan Capture Power Reduction
1343 -- 1347Hao Zheng, Jared Ahrens, Tian Xia. A Compositional Method With Failure-Preserving Abstraction for Asynchronous Design Verification