| 985 | -- | 998 | Chong-Fatt Law, Bah-Hwee Gwee, Joseph Sylvester Chang. Asynchronous Control Network Optimization Using Fast Minimum-Cycle-Time Analysis |
| 999 | -- | 1012 | Dong Xiang, Yang Zhao, Krishnendu Chakrabarty, Hideo Fujiwara. A Reconfigurable Scan Architecture With Weighted Scan-Enable Signals for Deterministic BIST |
| 1013 | -- | 1026 | Levent Aksoy, Eduardo da Costa, Paulo F. Flores, José Monteiro. Exact and Approximate Algorithms for the Optimization of Area and Delay in Multiple Constant Multiplications |
| 1027 | -- | 1040 | Javid Jaffari, Mohab Anis. Statistical Thermal Profile Considering Process Variations: Analysis and Applications |
| 1041 | -- | 1054 | Xin Li, Jiayong Le, Mustafa Celik, Lawrence T. Pileggi. Defining Statistical Timing Sensitivity for Logic Circuits With Large-Scale Process and Environmental Variations |
| 1055 | -- | 1065 | Zhe-Wei Jiang, Yao-Wen Chang. An Optimal Network-Flow-Based Simultaneous Diode and Jumper Insertion Algorithm for Antenna Fixing |
| 1066 | -- | 1077 | Jarrod A. Roy, Igor L. Markov. High-Performance Routing at the Nanometer Scale |
| 1078 | -- | 1090 | Pramod Chandraiah, Rainer Dömer. Code and Data Structure Partitioning for Parallel and Flexible MPSoC Specification Using Designer-Controlled Recoding |
| 1091 | -- | 1103 | Tarvo Raudvere, Ingo Sander, Axel Jantsch. Application and Verification of Local Nonsemantic-Preserving Transformations in System Design |
| 1104 | -- | 1116 | Wei-Shun Chuang, Shiu-Ting Lin, Wei-Chih Liu, James Chien-Mo Li. Diagnosis of Multiple Scan Chain Timing Faults |
| 1117 | -- | 1127 | S. Saqib Khursheed, Urban Ingelsson, Paul M. Rosinger, Bashir M. Al-Hashimi, Peter Harrod. Bridging Fault Test Method With Adaptive Power Management Awareness |
| 1128 | -- | 1137 | Afshin Abdollahi, Massoud Pedram. Symmetry Detection and Boolean Matching Utilizing a Signature-Based Canonical Form of Boolean Functions |
| 1138 | -- | 1149 | Görschwin Fey, Stefan Staber, Roderick Bloem, Rolf Drechsler. Automatic Fault Localization for Property Checking |
| 1150 | -- | 1154 | Brajesh Kumar Kaushik, Sankar Sarkar. Crosstalk Analysis for a CMOS-Gate-Driven Coupled Interconnects |
| 1155 | -- | 1159 | Sanghyun Park, Aviral Shrivastava, Nikil D. Dutt, Alexandru Nicolau, Yunheung Paek, Eugene Earlie. Register File Power Reduction Using Bypass Sensitive Compiler |
| 1159 | -- | 1164 | Lin Yuan, Gang Qu, Tiziano Villa, Alberto L. Sangiovanni-Vincentelli. An FSM Reengineering Approach to Sequential Circuit Synthesis by State Splitting |