| 205 | -- | 216 | Javid Jaffari, Mohab Anis. Variability-Aware Bulk-MOS Device Design |
| 217 | -- | 229 | R. Mahesh, A. Prasad Vinod. A New Common Subexpression Elimination Algorithm for Realizing Low-Complexity Higher Order Digital Filters |
| 230 | -- | 240 | Andrew B. Kahng, Sudhakar Muddu, Puneet Sharma. Defocus-Aware Leakage Estimation and Control |
| 241 | -- | 248 | Ja Chun Ku, Yehea I. Ismail. Area Optimization for Leakage Reduction and Thermal Stability in Nanometer-Scale Technologies |
| 249 | -- | 264 | Ning Dong, Jaijeet S. Roychowdhury. General-Purpose Nonlinear Model-Order Reduction Using Piecewise-Polynomial Representations |
| 265 | -- | 271 | Alexander Heldring, Juan M. Rius, José Maria Tamayo, Josep Parrón. Compressed Block-Decomposition Algorithm for Fast Capacitance Extraction |
| 272 | -- | 285 | Ashish Srivastava, Kaviraj Chopra, Saumil Shah, Dennis Sylvester, David Blaauw. A Novel Approach to Perform Gate-Level Yield Analysis and Optimization Considering Correlated Variations in Power and Performance |
| 286 | -- | 294 | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin. A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning |
| 295 | -- | 308 | Jaskirat Singh, Zhi-Quan Luo, Sachin S. Sapatnekar. A Geometric Programming-Based Worst Case Gate Sizing Method Incorporating Spatial Correlation |
| 309 | -- | 326 | Shantanu Dutt, Vinay Verma, Vishal Suthar. Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing |
| 327 | -- | 338 | Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker. On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing |
| 339 | -- | 351 | Haralampos-G. D. Stratigopoulos, Yiorgos Makris. Error Moderation in Low-Cost Machine-Learning-Based Analog/RF Testing |
| 352 | -- | 365 | Zhanglei Wang, Krishnendu Chakrabarty. Test-Quality/Cost Optimization Using Output-Deviation-Based Reordering of Test Patterns |
| 366 | -- | 379 | Himanshu Jain, Daniel Kroening, Natasha Sharygina, Edmund M. Clarke. Word-Level Predicate-Abstraction and Refinement Techniques for Verifying RTL Verilog |
| 380 | -- | 393 | Ilya Wagner, Valeria Bertacco, Todd M. Austin. Using Field-Repairable Control Logic to Correct Design Errors in Microprocessors |
| 394 | -- | 398 | Hiren D. Patel, Sandeep K. Shukla. On Cosimulating Multiple Abstraction-Level System-Level Models |
| 398 | -- | 403 | Irith Pomeranz, Sudhakar M. Reddy. Scan-Based Delay Test Types and Their Effect on Power Dissipation During Test |
| 403 | -- | 407 | Aleksandra Sesic, Stanisa Dautovic, Veljko Malbasa. Dynamic Power Management of a System With a Two-Priority Request Queue Using Probabilistic-Model Checking |