Journal: IEEE Trans. on CAD of Integrated Circuits and Systems

Volume 36, Issue 8

1237 -- 1250Wen-Hsiang Chang, Chien-Hsueh Lin, Szu-Pang Mu, Li-De Chen, Cheng-Hong Tsai, Yen-Chih Chiu, Mango C.-T. Chao. Generating Routing-Driven Power Distribution Networks With Machine-Learning Technique
1251 -- 1264Hsiao-Lei Chien, Mei-Yen Chiu, Jie-Hong R. Jiang. A Gridless Approach to the Satisfiability of Self-Aligned Triple Patterning
1265 -- 1273Shreepad Panth, Sandeep Kumar Samal, Kambiz Samadi, Yang Du, Sung Kyu Lim. Tier Degradation of Monolithic 3-D ICs: A Power Performance Study at Different Technology Nodes
1274 -- 1286Mark Po-Hung Lin, Vincent Wei-Hao Hsiao, Chun-Yu Lin, Nai-Chen Chen. Parasitic-Aware Common-Centroid Binary-Weighted Capacitor Layout Generation Integrating Placement, Routing, and Unit Capacitor Sizing
1287 -- 1300Qi Xu, Song Chen, Xiaodong Xu, Bei Yu. Clustered Fault Tolerance TSV Planning for 3-D Integrated Circuits
1301 -- 1312Daohang Shi, Edward Tashjian, Azadeh Davoodi. Dynamic Planning of Local Congestion From Varying-Size Vias for Global Routing Layer Assignment
1313 -- 1326Tsun-Ming Tseng, Bing Li, Ching-feng Yeh, Hsiang-Chieh Jhan, Zuo-Min Tsai, Mark Po-Hung Lin, Ulf Schlichtmann. An Efficient Two-Phase ILP-Based Algorithm for Precise CMOS RFIC Layout Generation
1327 -- 1339Ming Tang, Zhipeng Guo, Annelie Heuser, Yanzhen Ren, Jie Li, Jean-Luc Danger. PFD - A Flexible Higher-Order Masking Scheme
1340 -- 1352Edwin Hsing-Mean Sha, Congming Gao, Liang Shi, Kaijie Wu 0001, Mengying Zhao, Chun Jason Xue. Asymmetric Error Rates of Cell States Exploration for Performance Improvement on Flash Memory Based Storage Systems
1353 -- 1366Miao Hu, Yiran Chen, J. Joshua Yang, Yu Wang, Hai Helen Li. A Compact Memristor-Based Dynamic Synapse for Spiking Neural Networks
1367 -- 1380Vicky S. Kalogeiton, Dim P. Papadopoulos, Orestis Liolis, Vasilios A. Mardiris, Georgios Ch. Sirakoulis, Ioannis G. Karafyllidis. Programmable Crossbar Quantum-Dot Cellular Automata Circuits
1381 -- 1394Yixiao Ding, Chris Chu, Wai-Kei Mak. Self-Aligned Double Patterning Lithography Aware Detailed Routing With Color Preassignment
1395 -- 1405Xuan Dong, Lihong Zhang. Process-Variation-Aware Rule-Based Optical Proximity Correction for Analog Layout Migration
1406 -- 1419Ran Wang, Zipeng Li, Sukeshwar Kannan, Krishnendu Chakrabarty. Prebond Testing and Test-Path Design for the Silicon Interposer in 2.5-D ICs