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    Journal: IEEE Trans. on Circuits and Systems

    Volume 61-II, Issue 9

    641 -- 645Nadeem Afzal, J. Jacob Wikner, Oscar Gustafsson. Reducing Complexity and Power of Digital Multibit Error-Feedback ΔΣ Modulators
    646 -- 650Bongsub Song, Kyunghoon Kim, Junan Lee, Jinil Chung, Youngjung Choi, Jinwook Burm. A 13.5-mW 10-Gb/s 4-PAM Serial Link Transmitter in 0.13-µm CMOS Technology
    651 -- 655Xin Cheng, Guangjun Xie, Zhang Zhang, Yizhong Yang. Fast-Settling Feedforward Automatic Gain Control Based on a New Gain Control Approach
    656 -- 660Tin Wai Mui, Marco Ho, Kai Ho Mak, Jianping Guo, Hua Chen, Ka Nang Leung. An Area-Efficient 96.5%-Peak-Efficiency Cross-Coupled Voltage Doubler With Minimum Supply of 0.8 V
    661 -- 665Yu-Hsuan Chiang, Shen-Iuan Liu. Nanopower CMOS Relaxation Oscillators With Sub-100 ppm°C Temperature Coefficient
    666 -- 670Dai Zhang, Atila Alvandpour. Analysis and Calibration of Nonbinary-Weighted Capacitive DAC for High-Resolution SAR ADCs
    671 -- 675Padmanabhan Suryasarman, Peng Liu, Andreas Springer. Optimizing the Identification of Digital Predistorters for Improved Power Amplifier Linearization Performance
    676 -- 680Keum-Won Ha, Hyuk Ryu, Joonhong Park, Jeong Geun Kim, Donghyun Baek. Transformer-Based Current-Reuse Armstrong and Armstrong-Colpitts VCOs
    681 -- 685Shanthi Pavan, Radha S. Rajan. Simplified Analysis and Simulation of the STF, NTF, and Noise in Continuous-Time ΔΣ Modulators
    686 -- 690Shanthi Pavan, Radha S. Rajan. Interreciprocity in Linear Periodically Time-Varying Networks With Sampled Outputs
    691 -- 695Shengbo Zhang, Jun Xiao, Guangjun Yang, Jian Hu, Shichang Zou. A Novel Sourceline Voltage Compensation Circuit and a Wordline Voltage-Generating System for Embedded nor Flash Memory
    696 -- 700Yadong Yin, Yuepeng Yan, Chenjun Wei, Shaodan Yang. A Low-Power Low-Cost GFSK Demodulator With a Robust Frequency Offset Tolerance
    701 -- 705Taeho Seong, Yongsun Lee, Jaehyouk Choi. Ultralow In-Band Phase Noise Injection-Locked Frequency Multiplier Design Based on Open-Loop Frequency Calibration
    706 -- 710Myat Thu Linn Aung, Eric Lim, Takefumi Yoshikawa, Tony Tae-Hyoung Kim. A 3-Gb/s/ch Simultaneous Bidirectional Capacitive Coupling Transceiver for 3DICs
    711 -- 715Dong Wang, Jean-Michel Muller, Nicolas Brisebarre, Milos D. Ercegovac. (M, p, k)-Friendly Points: A Table-Based Method to Evaluate Trigonometric Function
    716 -- 720Muhammad Imran, Abdul Ghafoor. Stability Preserving Model Reduction Technique and Error Bounds Using Frequency-Limited Gramians for Discrete-Time Systems
    721 -- 725Mohammad Ali Pakzad, Mohammad Ali Nekoui. Stability Analysis of Linear Time-Invariant Fractional Exponential Delay Systems
    726 -- 730Sai Zhang, Naresh R. Shanbhag, Philip T. Krein. t Computing

    Volume 61-II, Issue 7

    461 -- 465Arindam Sanyal, Peijun Wang, Nan Sun. A Thermometer-Like Mismatch Shaping Technique With Minimum Element Transition Activity for Multibit $\Delta\Sigma$ DACs
    466 -- 470Annachiara Spagnolo, Bob Verbruggen, Piet Wambacq, Stefano D'Amico. A 4.1-mW 3.5-GS/s 6-Bit Time-Interleaved ADC in 40-nm CMOS
    471 -- 475Yun Yin, Baoyong Chi, Zhaokang Xia, Zhihua Wang. A Reconfigurable Dual-Mode CMOS Power Amplifier With Integrated T/R Switch for 0.1-1.5-GHz Multistandard Applications
    476 -- 480Lei Sun, Chi-Tung Ko, Kong-Pang Pun. Optimizing the Stage Resolution in Pipelined SAR ADCs for High-Speed High-Resolution Applications
    481 -- 485Hye-Jung Kwon, Jae-Seung Lee, Byungsub Kim, Jae-Yoon Sim, Hong June Park. Analysis of an Open-Loop Time Amplifier With a Time Gain Determined by the Ratio of Bias Current
    486 -- 490Jing Li, Shuangyi Wu, Yang Liu, Ning Ning, Qi Yu. A Digital Timing Mismatch Calibration Technique in Time-Interleaved ADCs
    491 -- 495Zdenek Biolek, Dalibor Biolek. How Can the Hysteresis Loop of the Ideal Memristor Be Pinched?
    496 -- 500Jerrin Pathrose, Lei Zou, Kevin T. C. Chai, Minkyu Je, Yong Ping Xu. Temperature Sensor Front End in SOI CMOS Operating up to 250 $^{\circ}\hbox{C}$
    501 -- 505Golsa Moayeri Pour, Mohammad K. Benyhesan, Walter D. Leon-Salas. Energy Harvesting Using Substrate Photodiodes
    506 -- 510Alexander Edward, José Silva-Martínez. General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators
    511 -- 515Sang Yoon Park, Pramod Kumar Meher. Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter
    516 -- 520Quan Xu, Thomas M. Chen, Yupeng Hu, Pu Gong. Write Pattern Format Algorithm for Reliable NAND-Based SSDs
    521 -- 525Manish Kumar Jaiswal, Ray C. C. Cheung, M. Balakrishnan, Kolin Paul. Unified Architecture for Double/Two-Parallel Single Precision Floating Point Adder
    526 -- 530Davide De Caro, Mariangela Genovese, Ettore Napoli, Nicola Petra, Antonio G. M. Strollo. Accurate Fixed-Point Logarithmic Converter
    531 -- 535Chunguo Li, Fan Sun, John M. Cioffi, Luxi Yang. Energy Efficient MIMO Relay Transmissions via Joint Power Allocations
    536 -- 540Sheng Zhang, Jiashu Zhang. Set-Membership NLMS Algorithm With Robust Error Bound
    541 -- 545Lan Gao, Xiaofeng Liao, Huaqing Li. Pinning Controllability Analysis of Complex Networks With a Distributed Event-Triggered Mechanism

    Volume 61-II, Issue 6

    373 -- 377Zheng Gao, Ping Gui, Rick Jordanger. An Integrated High-Voltage Low-Distortion Current-Feedback Linear Power Amplifier for Ultrasound Transmitters Using Digital Predistortion and Dynamic Current Biasing Techniques
    378 -- 382David Gaied, Emad Hegazi. Charge-Pump Folded Noise Cancelation in Fractional-N Phase-Locked Loops
    383 -- 387Francisco Colodro, Antonio Torralba. Linearity Enhancement of VCO-Based Quantizers for SD Modulators by Means of a Tracking Loop
    388 -- 392Matthias Lorenz, Rudolf Ritter, Joachim Becker, Maurits Ortmanns. A Genetic Algorithm for the Estimation of Nonidealities in Continuous-Time Sigma-Delta Modulators
    393 -- 397Gitae Pyo, Jaemo Yang, Choul-Young Kim, Songcheol Hong. K-Band Dual-Mode Receiver CMOS IC for FMCW/UWB Radar
    398 -- 402Adi Xhakoni, Georges G. E. Gielen. A 132-dB Dynamic-Range Global-Shutter Stacked Architecture for High-Performance Imagers
    403 -- 407Lin He, Yuncheng Zhang, Fang Long, Fengcheng Mei, Mingyuan Yu, Fujiang Lin, Libin Yao, Xicheng Jiang. Digital Noise-Coupling Technique for Delta-Sigma Modulators With Segmented Quantization
    408 -- 412Younghoon Kim, Changsik Yoo. A 100-kS/s 8.3-ENOB 1.7- µW Time-Domain Analog-to-Digital Converter
    413 -- 417Hamed Aminzadeh, Mohammad R. Nabavi, Wouter A. Serdijn. Low-Dropout Voltage Source: An Alternative Approach for Low-Dropout Voltage Regulators
    418 -- 422Basant Kumar Mohanty, Sujit Kumar Patel. Area-Delay-Power Efficient Carry-Select Adder
    423 -- 427Zheng Yu, Zhiyi Yu, Xueqiu Yu, Ningxi Liu, Xiaoyang Zeng. Low-Power Multicore Processor Design With Reconfigurable Same-Instruction Multiple Process
    428 -- 432Sumit Jagdish Darak, A. Prasad Vinod, Edmund Ming-Kit Lai, Jacques Palicot, H. Zhang. Linear-Phase VDF Design With Unabridged Bandwidth Control Over the Nyquist Band
    433 -- 437Anand D. Darji, Shubham Agrawal, Ankit Oza, Vipul Sinha, Aditya Verma, S. N. Merchant, Arun N. Chandorkar. Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform
    438 -- 442Seok Kim, Eun-Young Jin, Kee-Won Kwon, Jintae Kim, Jung-Hoon Chun. A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE
    443 -- 447Asma Maalej, Manel Ben-Romdhane, Chiheb Rebai, Adel Ghazel, Patricia Desgreys, Patrick Loumeau. Toward Time-Quantized Pseudorandom Sampling for Green Communication
    448 -- 452Haiyan Shu, Rongshan Yu, Wenyu Jiang, Wenxian Yang. Efficient Implementation of $k$-Nearest Neighbor Classifier Using Vote Count Circuit
    453 -- 457Xi-Ming Sun, Di Wu, Changyun Wen, Wei Wang 0036. A Novel Stability Analysis for Networked Predictive Control Systems

    Volume 61-II, Issue 5

    289 -- 293Heein Yoon, Yongsun Lee, Jae-Joon Kim, Jaehyouk Choi. A Wideband Dual-Mode LC-VCO With a Switchable Gate-Biased Active Core
    294 -- 298Arindam Sanyal, Nan Sun. An Energy-Efficient Low Frequency-Dependence Switching Technique for SAR ADCs
    299 -- 303Y. Liang, H. Chen, D. S. Yu. A Practical Implementation of a Floating Memristor-Less Meminductor Emulator
    304 -- 308Taeho Kim, Sungchun Jang, SungWoo Kim, Sang-Hyeok Chu, Jiheon Park, Deog Kyoon Jeong. A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process
    309 -- 313Carlos Sánchez-López, Jorge Mendoza-Lopez, Miguel Ángel Carrasco-Aguilar, Carlos Muniz-Montero. A Floating Analog Memristor Emulator Circuit
    314 -- 318Jia Mao, Zhuo Zou, Li-Rong Zheng. A Subgigahertz UWB Transmitter With Wireless Clock Harvesting for RF-Powered Applications
    319 -- 323Joung-Wook Moon, Kwang-Chun Choi, Woo-Young Choi. A 0.4-V, 90 ∼ 350-MHz PLL With an Active Loop-Filter Charge Pump
    324 -- 328Lianxi Liu, Shijie Deng, Zhangming Zhu, Yintang Yang. A 2.1-Channel Class-D Amplifier Exploited Coupling Virtual-Audio-Image to Enhance Stereo
    329 -- 333Byoungho Kim, Jacob A. Abraham. Dynamic Performance Characterization of Embedded Single-Ended Mixed-Signal Circuits
    334 -- 338Kuo-Ken Huang, David D. Wentzloff. A 1.2-MHz 5.8-µW Temperature-Compensated Relaxation Oscillator in 130-nm CMOS
    339 -- 343Hung-Yen Tai, Cheng-Hsueh Tsai, Pao-Yang Tsai, Hung-Wei Chen, Hsin-Shu Chen. A 6-bit 1-GS/s Two-Step SAR ADC in 40-nm CMOS
    344 -- 348Amit Ranjan Trivedi, Wen Yueh, Saibal Mukhopadhyay. In Situ Power Gating Efficiency Learner for Fine-Grained Self-Adaptive Power Gating
    349 -- 353Abdelkrim Kamel Oudjida, Nicolas Chaillet. r Arithmetic for Multiplication by a Constant
    354 -- 358Jiangpeng Li, Kai Zhao, Jun Ma, Tong Zhang 0002. Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead
    359 -- 363Guanghui Wen, Guoqiang Hu, Wenwu Yu, Guanrong Chen. ∞ Consensus of Higher Order Multiagent Systems With Switching Topologies
    364 -- 367Walter J. Kozacky, Tokunbo Ogunfunmi. Convergence Analysis of an Adaptive Algorithm With Output Power Constraints
    368 -- 372Chien-Cheng Tseng, Su-Ling Lee. On the Designs of Variable Fractional Hilbert Transformers

    Volume 61-II, Issue 4

    209 -- 213Shuai Yuan, Ziqiang Wang, Xuqiang Zheng, Ke Huang, Ni Xu, Woogeun Rhee, Liji Wu, Chun Zhang. A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS
    214 -- 218Ekaterina Panina, Lucio Pancheri, Gian-Franco Dalla Betta, Nicola Massari, David Stoppa. Compact CMOS Analog Counter for SPAD Pixel Arrays
    219 -- 223Taner Sumesaglam. An 11-Gb/s Receiver With a Dynamic Linear Equalizer in a 22-nm CMOS
    224 -- 228Jaejin Yeo, Yongsuk Choi, Jeongjin Roh, Gunhee Han, Youngcheol Chae, Seogheon Ham. A Current Regulator for Inverter-Based Massively Column-Parallel $\Delta \Sigma$ ADCs
    229 -- 233YoungHyun Yoon, Hyungdong Roh, Jeongjin Roh. A True 0.4-V Delta-Sigma Modulator Using a Mixed DDA Integrator Without Clock Boosted Switches
    234 -- 238Kim B. Ostman, Jani K. Jarvenhaara, Svetozar S. Broussev, Ismo Viitaniemi. A 3.6-to-1.8-V Cascode Buck Converter With a Stacked $LC$ Filter in 65-nm CMOS
    239 -- 243Kang-Sub Kwak, Oh-Kyong Kwon. Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits
    244 -- 248Weibo Li, Yoshitaka Niimi, Yuichiro Orino, Shinnosuke Hirata, Minoru Kuribayashi Kurosawa. A Frequency Synchronization Method for a Self-Oscillating PWM Signal Generator
    249 -- 253Antonino M. Sommariva. On Brune's Tests
    254 -- 258Jack Shiah, Shahriar Mirabbasi. A 5-V 290-µW Low-Noise Chopper-Stabilized Capacitive-Sensor Readout Circuit in 0.8-µm CMOS Using a Correlated-Level-Shifting Technique
    259 -- 263Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg. Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM
    264 -- 268Jianhui Wu, Jiafeng Zhu, YingCheng Xia, Na Bai. A Multiple-Stage Parallel Replica-Bitline Delay Addition Technique for Reducing Timing Variation of SRAM Sense Amplifiers
    269 -- 273Toshihiro Hori. Novel One-Dimensional Sampling Method to Calculate Two-Dimensional Diamond-Shaped Discrete Frequency Distributions
    274 -- 278JinWoo Yoo, Jaewook Shin, PooGyeon Park. Variable Step-Size Affine Projection Sign Algorithm
    279 -- 283Chamira U. S. Edussooriya, Len T. Bruton, Mehdi Ataei Naeini, Panajotis Agathoklis. Using 1-D Variable Fractional-Delay Filters to Reduce the Computational Complexity of 3-D Broadband Multibeam Beamformers
    284 -- 288Soo-Chang Pei, Chia-Chang Wen, Jian-Jiun Ding. Conjugate Symmetric Discrete Orthogonal Transform

    Volume 61-II, Issue 3

    133 -- 137Ken-Fu Liang, Jau-Horng Chen, Yi-Jan Emery Chen. A Quadratic-Interpolated LUT-Based Digital Predistortion Technique for Cellular Power Amplifiers
    138 -- 142Fang Zhu, Wei Hong, Jixin Chen, Xin Jiang, Ke Wu, Pinpin Yan, Chun-Lin Han. A Broadband Low-Power Millimeter-Wave CMOS Downconversion Mixer With Improved Linearity
    143 -- 147Nicola Da Dalt. An Analysis of Phase Noise in Realigned VCOs
    148 -- 152Dennis R. Morgan. Combined Three-State/PWM Signal Coding for Wideband High-Efficiency Class-S Amplifiers
    153 -- 157Sang-Hye Chung, Young-Ju Kim, Kyung-Soo Ha, Seung-Jun Bae, Jung-Bae Lee, Lee-Sup Kim. A Forwarded-Clock Receiver With Constant and Wide-Range Jitter-Tracking Bandwidth
    158 -- 162Michele Bonnin, Fernando Corinto. Influence of Noise on the Phase and Amplitude of Second-Order Oscillators
    163 -- 167Chun-Chi Chen, Shih-Hao Lin, Chorng-Sii Hwang. An Area-Efficient CMOS Time-to-Digital Converter Based on a Pulse-Shrinking Scheme
    168 -- 172Antonio C. C. Telles, Saulo Finco, Jose Antenor Pomilio. Modeling of a MOS Ultralow Voltage Astable Multivibrator for Energy Harvesting
    173 -- 177Kwanyeob Chae, Saibal Mukhopadhyay. Resilient Pipeline Under Supply Noise With Programmable Time Borrowing and Delayed Clock Gating
    178 -- 182Xuelian Liu, Srikumar Raman, Ryan Clarke, Mitchell R. LeRoy, Okan Erdogan, Michael Chu, Alexey Gutin, Russell P. Kraft, John F. McDonald. Design of High-Speed Register Files Using SiGe HBT BiCMOS Technology
    183 -- 187Bishnu Prasad Das, Hidetoshi Onodera. On-Chip Measurement of Rise/Fall Gate Delay Using Reconfigurable Ring Oscillator
    188 -- 192Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, Wei Hwang. Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
    193 -- 197Jisu Kim, Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung. A Split-Path Sensing Circuit for Spin Torque Transfer MRAM
    198 -- 202Jeevan K. Pant, Wu-Sheng Lu, Andreas Antoniou. New Improved Algorithms for Compressive Sensing Based on $\ell_{p}$ Norm
    203 -- 207Shunsuke Koshita, Masahide Abe, Masayuki Kawamata. A Simple Ladder Realization of Maximally Flat Allpass Fractional Delay Filters

    Volume 61-II, Issue 2

    65 -- 69Tolga Dinc, Ilker Kalyoncu, Yasar Gurbuz. An X-Band Slow-Wave T/R Switch in 0.25-$\mu\hbox{m}$ SiGe BiCMOS
    70 -- 74Kim B. Ostman, Mikko Englund, Olli Viitala, Kari Stadius, Kimmo Koli, Jussi Ryynänen. Characteristics of LNA Operation in Direct Delta-Sigma Receivers
    75 -- 79Chen-Chien Lin, Chan-Hsiang Weng, Tzu-An Wei, Yung-Yu Lin, Tsung-Hsien Lin. A TDC-Based Two-Step Quantizer With Swapper Technique for a Multibit Continuous-Time Delta-Sigma Modulator
    80 -- 84Bozorgmehr Vosooghi, Li Lu, Changzhi Li. Leakage, Area, and Headroom Tradeoffs for Scattered Relative Temperature Sensor Front-End Architectures
    85 -- 89Goran Molnar, Mladen Vucic. Bernoulli Low-Pass Filters
    90 -- 94Jordi Perez-Puigdemont, Francesc Moll, Antonio Calomarde. All-Digital Simple Clock Synthesis Through a Glitch-Free Variable-Length Ring Oscillator
    95 -- 99Chun-Fu Liao, Fang-Chun Lan, Jin-Wei Jhang, Yuan-Hao Huang. A 576-Mbit/s 64-QAM 4 $\times$ 4 MIMO Precoding Processor With Lattice Reduction
    100 -- 104K. Subburaj, S. Bhatara, J. Tangudu, J. R. Samuel, R. Ganesan, K. Ramasubramanian. Spur Mitigation in High-Sensitivity GNSS Receivers
    105 -- 109Ashkan Ashrafi. Optimization of the Quantized Coefficients for DDFS Utilizing Polynomial Interpolation Methods
    110 -- 114Weihua Zheng, Kenli Li, Keqin Li. A Fast Algorithm Based on SRFFT for Length $N = q\times 2^{m}$ DFTs
    115 -- 119Chuan Zhang, Keshab K. Parhi. Latency Analysis and Architecture Design of Simplified SC Polar Decoders
    120 -- 124Jangwon Park, Jongsun Park, Swarup Bhunia. VL-ECC: Variable Data-Length Error Correction Code for Embedded Memory in DSP Applications
    125 -- 129Siavash Bayat Sarmadi, Mehran Mozaffari Kermani, Reza Azarderakhsh, Chiou-Yng Lee. Dual-Basis Superserial Multipliers for Secure Applications and Lightweight Cryptographic Architectures

    Volume 61-II, Issue 12

    917 -- 921Haikun Jia, Baoyong Chi, Lixue Kuang, Zhihua Wang. A 38- to 40-GHz Current-Reused Active Phase Shifter Based on the Coupled Resonator
    922 -- 926Peter Sjöblom, Henrik Sjöland. Constant Mismatch Loss Boundary Circles and Their Application to Optimum State Distribution in Adaptive Matching Networks
    927 -- 931Zhiwen Zhu, Xinping Huang, Henry Leung. Compensation of Delay Mismatch in a Direct Conversion Transmitter
    932 -- 936Xican Chen, Wei Zhang, Woogeun Rhee, Zhihua Wang. A ΔΣ-TDC-Based Beamforming Method for Vital Sign Detection Radar Systems
    937 -- 941Stewart Robson, Bosco Leung, Guang Gong. Truly Random Number Generator Based on a Ring Oscillator Utilizing Last Passage Time
    942 -- 946Soon-Jae Kweon, Soo-Hwan Shin, Sung-Hun Jo, Hyung-Joun Yoo. Reconfigurable High-Order Moving-Average Filter Using Inverter-Based Variable Transconductance Amplifiers
    947 -- 951Shien-Chun Luo, Kuo-Chiang Chang, Ming-Pin Chen, Ching-Ji Huang, Yi-Fang Chiu, Po-Hsun Chen, Liang-Chia Cheng, Chih-Wei Liu, Yuan-Hua Chu. Separate Clock Network Voltage for Correcting Random Errors in ULV Clocked Storage Cells
    952 -- 956Daniel Gomez Toro, Matthieu Arzel, Fabrice Seguin, Michel Jézéquel. Soft Error Detection and Correction Technique for Radiation Hardening Based on C-element and BICS
    957 -- 961Meng-chou Chang, Ming-Hsun Hsieh, Po-Hung Yang. Low-Power Asynchronous NCL Pipelines With Fine-Grain Power Gating and Early Sleep
    962 -- 966Fei Xiao. Fast Design of IIR Digital Filters With a General Chebyshev Characteristic
    967 -- 971Hua Yang, Guo-Ping Jiang, Junyi Duan. Phase-Separated DCSK: A Simple Delay-Component-Free Solution for Chaotic Communications
    972 -- 976Georgios Papandroulidakis, Ioannis Vourkas, Nikolaos Vasileiadis, Georgios Ch. Sirakoulis. Boolean Logic Operations and Computing Circuits Based on Memristors
    977 -- 981Chunbiao Li, Julien Clinton Sprott, Wesley Thio, Huanqiang Zhu. A New Piecewise Linear Hyperchaotic Circuit
    982 -- 986Luigi Alfredo Grieco, Mahdi Ben Alaya, Thierry Monteil, Khalil Drira. A Dynamic Random Graph Model for Diameter-Constrained Topologies in Networked Systems
    987 -- 991Il-Min Yi, Soo-Min Lee, Seung-Jun Bae, Young-Soo Sohn, Jung Hwan Choi, Byungsub Kim, Jae-Yoon Sim, Hong June Park. A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination
    992 -- 996Yun Chen, Qichen Zhang, Di Wu, Changsheng Zhou, Xiaoyang Zeng. An Efficient Multirate LDPC-CC Decoder With a Layered Decoding Algorithm for the IEEE 1901 Standard
    997 -- 1001Bing Yuan, Xinquan Lai, Hongyi Wang, Qiang Ye. Pseudo-Type-III Compensation Integrated in a Voltage-Mode Buck Regulator
    1002 -- 1006Andres A. Blanco, Gabriel A. Rincón-Mora. A 44-93-µs 250-400-mV 0.18-µm CMOS Starter for DC-Sourced Switched-Inductor Energy Harvesters

    Volume 61-II, Issue 11

    825 -- 829Jen-Huan Tsai, Hui-Huan Wang, Yen-Ju Chen, Yen-Hsin Wei, Yo-Hsien Kao, Yang-Chi Yen, Po-Chiun Huang, Meng-Hung Shen, Hsin Chen. A 1-V-0.6-V 9-b 1.5-MS/s Reference-Free Charge-Sharing SAR ADC for Wireless-Powered Implantable Telemetry
    830 -- 834Haoyu Zhuang, Zhangming Zhu, Yintang Yang. A 19-nW 0.7-V CMOS Voltage Reference With No Amplifiers and No Clock Circuits
    835 -- 839Stefan Hänzsche, Sebastian Höppner, Georg Ellguth, René Schüffny. A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology
    840 -- 844Hyunsoo Ha, Seon-Kyoo Lee, Byungsub Kim, Hong June Park, Jae-Yoon Sim. A 0.5-V, 1.47- µW 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation
    845 -- 849Yu-Hsun Chien, Kuan-Lin Fu, Shen-Iuan Liu. A 3-25 Gb/s Four-Channel Receiver With Noise-Canceling TIA and Power-Scalable LA
    850 -- 854Byung-Do Yang. 250-mV Supply Subthreshold CMOS Voltage Reference Using a Low-Voltage Comparator and a Charge-Pump Circuit
    855 -- 859Juan Antonio Leñero-Bardallo, Philipp Häfliger. A Dual-Operation-Mode Bio-Inspired Pixel
    860 -- 864Pavel Angelov, Syed Ahmed Aamir, J. Jacob Wikner. A 1.1-V Analog Multiplexer With an Adaptive Digital Clamp for CMOS Video Digitizers
    865 -- 869Junyoung Song, Sewook Hwang, Hyun-Woo Lee, Chulwoo Kim. A 7.5-Gb/s Referenceless Transceiver With Adaptive Equalization and Bandwidth-Shifting Technique for Ultrahigh-Definition Television in a 0.13- µm CMOS Process
    870 -- 874Kin Keung Lee, Tor Sverre Lande. A Wireless-Powered IR-UWB Transmitter for Long-Range Passive RFID Tags in 90-nm CMOS
    875 -- 879Metin Sengül. Design of Practical Broadband Matching Networks With Mixed Lumped and Distributed Elements
    880 -- 884Jaehyeok Yang, Joon-Yeong Lee, Sun-Jae Lim, Hyeon-Min Bae. Phase-Rotator-Based All-Digital Phase-Locked Loop for a Spread-Spectrum Clock Generator
    885 -- 889Kai Zhao, Jiangpeng Li, Jun Ma, Rino Micheloni, Tong Zhang 0002. Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs
    890 -- 894Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini. A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values
    895 -- 899Shahar Kvatinsky, Dmitry Belousov, Slavik Liman, Guy Satat, Nimrod Wald, Eby G. Friedman, Avinoam Kolodny, Uri C. Weiser. MAGIC - Memristor-Aided Logic
    900 -- 904Tao Wang, Hsiao-Dong Chiang. On the Global Convergence of a Class of Homotopy Methods for Nonlinear Circuits and Systems
    905 -- 909Matteo Biggio, Federico Bizzarri, Angelo Brambilla, Marco Storace. Accurate and Efficient PSD Computation in Mixed-Signal Circuits: A Time-Domain Approach
    910 -- 914Abdelali El Aroudi. Prediction of Subharmonic Oscillation in Switching Converters Under Different Control Strategies
    915 -- 0Giovanni Russo, Mario di Bernardo. Correction to Section V-B of "Contraction Theory and the Master Stability Function: Linking Two Approaches to Study Synchronization in Complex Networks"

    Volume 61-II, Issue 10

    733 -- 737Chadi Jabbour, Hussein Fakhoury, Van Tam Nguyen, Patrick Loumeau. Delay-Reduction Technique for DWA Algorithms
    738 -- 742Mostafa A. N. Haroun, Anas A. Hamoui. Design and Verification of a Switchable Opamp for Switched-Capacitor Integrators
    743 -- 747Byoungho Kim, Jacob A. Abraham. Bitstream-Driven Built-In Characterization for Analog and Mixed-Signal Embedded Circuits
    748 -- 752Yeong-Shin Jang, Young-Hun Ko, Jung Min Choi, Hyung-Seog Oh, Sang-Gug Lee. A 45-dB, 150-Hz, and 18-mW Touch Controller for On-Cell Capacitive TSP Systems
    753 -- 757S. Rasool Hosseini, Mehdi Saberi, Reza Lotfi. A Low-Power Subthreshold to Above-Threshold Voltage Level Shifter
    758 -- 762Dongsheng Yu, Yan Liang, Herbert H. C. Iu, Leon O. Chua. A Universal Mutator for Transformations Among Memristor, Memcapacitor, and Meminductor
    763 -- 767Xiaofeng He, Xi Zhu, Lian Duan, Yichuang Sun, Chengyan Ma. A 14-mW PLL-Less Receiver in 0.18- $\mu\hbox{m}$ CMOS for Chinese Electronic Toll Collection Standard
    768 -- 772Ching-Yun Chu, Yu-Jiu Wang. A PVT-Independent Constant- $G_{m}$ Bias Technique Based on Analog Computation
    773 -- 777Niklas U. Andersson, Mark Vesterbacka. A Vernier Time-to-Digital Converter With Delay Latch Chain Architecture
    778 -- 782Miona Andrejevic Stosovic, Jaroslav M. Zivanic, Vanco B. Litovski. Maximally Flat Filter Functions With the Maximum Number of Transmission Zeros Having Maximal Multiplicity
    783 -- 787Jack Ou, Pietro M. Ferreira. A $g_{m}/I_{D}$-Based Noise Optimization for CMOS Folded-Cascode Operational Amplifier
    788 -- 792Mohammad Reza Keshtkaran, Zhi Yang. A Robust Adaptive Power Line Interference Canceler VLSI Architecture and ASIC for MultichannelBiopotential Recording Applications
    793 -- 797Chuan Zhang, Zhongfeng Wang, Xiaohu You. Efficient Decoder Architecture for Single Block-Row Quasi-Cyclic LDPC Codes
    798 -- 802Sadegh Yazdanshenas, Hossein Asadi. Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices
    803 -- 807Vladan Popovic, Elieva Pignat, Yusuf Leblebici. Performance Optimization and FPGA Implementation of Real-Time Tone Mapping
    808 -- 812Tomasz Podsiadlik, Ronan Farrell. Time-Interleaved $\Sigma\Delta$ Modulators for FPGAs
    813 -- 817Wei Xu, Jiaxiang Zhao, Chao Gu. Design of Linear-Phase FIR Multiple-Notch Filters via an Iterative Reweighted OMP Scheme
    818 -- 822Ting Zuo, Kehui Sun, Xingxing Ai, Huihai Wang. High-Order Grid Multiscroll Chaotic Attractors Generated by the Second-Generation Current Conveyor Circuit

    Volume 61-II, Issue 1

    1 -- 5Kyungho Ryu, Dong-Hoon Jung, Seong-Ook Jung. Process-Variation-Calibrated Multiphase Delay Locked Loop With a Loop-Embedded Duty Cycle Corrector
    6 -- 10Ghil-Geun Oh, Chang-Kyo Lee, Seung-Tak Ryu. A 10-Bit 40-MS/s Pipelined ADC With a Wide Range Operating Temperature for WAVE Applications
    11 -- 15Guanhua Wang, Foti Kacani, Yun Chiu. IRD Digital Background Calibration of SAR ADC With Coarse Reference ADC Acceleration
    16 -- 20I-Ting Lee, Shih-Han Ku, Shen-Iuan Liu. An All-Digital Despreading Clock Generator
    21 -- 25P. Stoliar, P. Levy, M. J. Sanchez, A. G. Leyva, C. A. Albornoz, F. Gomez-Marlasca, A. Zanini, C. Toro Salazar, N. Ghenzi, M. J. Rozenberg. Nonvolatile Multilevel Resistive Switching Memory Cell: A Transition Metal Oxide-Based Circuit
    26 -- 30Roghayeh Saeidi, Mohammad Sharifkhani, Khosro Hajsadeghi. A Subthreshold Symmetric SRAM Cell With High Read Stability
    31 -- 35Tao Li, Qing Zhao, James Lam, Zhiguang Feng. Multi-Bound-Dependent Stability Criterion for Digital Filters With Overflow Arithmetics and Time Delay
    36 -- 40Hai Huyen Dam. Variable Fractional Delay FIR Filter Design with a Bicriteria and Coefficient Relationship
    41 -- 43Jinwang Liu, Dongmei Li, Licui Zheng. The Lin-Bose Problem
    44 -- 48Maurizio Porfiri. Linear Analysis of the Vectorial Network Model
    49 -- 53Jun Yang, Wei Xing Zheng. Offset-Free Nonlinear MPC for Mismatched Disturbance Attenuation With Application to a Static Var Compensator
    54 -- 58Yutaro Yamashita, Hiroyuki Torikai. Theoretical Analysis for Efficient Design of a Piecewise Constant Spiking Neuron Model
    59 -- 63Chang-Chun Hua, Dan Liu, Xin-Ping Guan. Necessary and Sufficient Stability Criteria for a Class of Fractional-Order Delayed Systems
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