| 0 | -- | 0 | Ronny Krashinsky, Christopher Batten, Krste Asanovic. Implementing the scale vector-thread processor |
| 0 | -- | 0 | Alex K. Jones, Robert Walker. Introduction to the special section on demonstrable software systems and hardware platforms II |
| 0 | -- | 0 | Prabhat Mishra, Nikil Dutt. Specification-driven directed test generation for validation of pipelined processors |
| 0 | -- | 0 | Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Timothy Sherwood. Designing secure systems on reconfigurable hardware |
| 0 | -- | 0 | Nicola Bombieri, Franco Fummi, Graziano Pravadelli. Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow |
| 0 | -- | 0 | Panagiotis Manolios, Sudarshan K. Srinivasan. Automatic verification of safety and liveness for pipelined machines using WEB refinement |
| 0 | -- | 0 | Yongsoo Joo, Youngjin Cho, Donghwa Shin, Jaehyun Park, Naehyuck Chang. An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory |
| 0 | -- | 0 | Nikil D. Dutt. Editorial |
| 0 | -- | 0 | Sabyasachi Das, Sunil P. Khatri. Resource sharing among mutually exclusive sum-of-product blocks for area reduction |
| 0 | -- | 0 | Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek. A retargetable parallel-programming framework for MPSoC |
| 0 | -- | 0 | Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek. Evolution of synthetic RTL benchmark circuits with predefined testability |
| 0 | -- | 0 | Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor. Combining system scenarios and configurable memories to tolerate unpredictability |
| 0 | -- | 0 | Ozcan Ozturk, Mahmut T. Kandemir. ILP-Based energy minimization techniques for banked memories |
| 0 | -- | 0 | Hiroaki Inoue, Junji Sakai, Masato Edahiro. Processor virtualization for secure mobile terminals |
| 0 | -- | 0 | I-Lun Tseng, Adam Postula. Partitioning parameterized 45-degree polygons with constraint programming |
| 0 | -- | 0 | Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty. Power-aware SoC test planning for effective utilization of port-scalable testers |
| 0 | -- | 0 | Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal. Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA |
| 0 | -- | 0 | Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti. Postplacement voltage assignment under performance constraints |