Journal: ACM Trans. Design Autom. Electr. Syst.

Volume 13, Issue 4

0 -- 0Javier Resano, Juan Antonio Clemente, Carlos Gonzalez, Daniel Mozos, Francky Catthoor. Efficiently scheduling runtime reconfigurations
0 -- 0Michael D. Moffitt, Jarrod A. Roy, Igor L. Markov, Martha E. Pollack. Constraint-driven floorplan repair
0 -- 0S. K. Panda, Arnab Roy, P. P. Chakrabarti, Rajeev Kumar. Simulation-based verification using Temporally Attributed Boolean Logic
0 -- 0Ozcan Ozturk, Mahmut T. Kandemir, Guangyu Chen. Access pattern-based code compression for memory-constrained systems
0 -- 0Massoud Pedram. Editorial
0 -- 0Muhammet Mustafa Ozdal, Martin D. F. Wong, Philip S. Honsinger. Optimal routing algorithms for rectilinear pin clusters in high-density multichip modules
0 -- 0Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti. Auxiliary state machines + context-triggered properties in verification
0 -- 0Nastaran Baradaran, Pedro C. Diniz. A compiler approach to managing storage and memory bandwidth in configurable architectures
0 -- 0Konstantin Moiseev, Avinoam Kolodny, Shmuel Wimer. Timing-aware power-optimal ordering of signals
0 -- 0Sying-Jyan Wang, Kuo-Lin Peng, Kuang-Cyun Hsiao, Katherine Shu-Min Li. Layout-aware scan chain reorder for launch-off-shift transition test coverage
0 -- 0Nan Guan, Qingxu Deng, Zonghua Gu, Wenyao Xu, Ge Yu. Schedulability analysis of preemptive and nonpreemptive EDF on partial runtime-reconfigurable FPGAs
0 -- 0Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu. Effective decap insertion in area-array SoC floorplan design
0 -- 0Siddharth Garg, Diana Marculescu. System-level throughput analysis for process variation aware multiple voltage-frequency island designs
0 -- 0Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal. A high-level clustering algorithm targeting dual V::dd:: FPGAs

Volume 13, Issue 3

0 -- 0Ronny Krashinsky, Christopher Batten, Krste Asanovic. Implementing the scale vector-thread processor
0 -- 0Alex K. Jones, Robert Walker. Introduction to the special section on demonstrable software systems and hardware platforms II
0 -- 0Prabhat Mishra, Nikil Dutt. Specification-driven directed test generation for validation of pipelined processors
0 -- 0Ted Huffmire, Brett Brotherton, Nick Callegari, Jonathan Valamehr, Jeff White, Ryan Kastner, Timothy Sherwood. Designing secure systems on reconfigurable hardware
0 -- 0Nicola Bombieri, Franco Fummi, Graziano Pravadelli. Reuse and optimization of testbenches and properties in a TLM-to-RTL design flow
0 -- 0Panagiotis Manolios, Sudarshan K. Srinivasan. Automatic verification of safety and liveness for pipelined machines using WEB refinement
0 -- 0Yongsoo Joo, Youngjin Cho, Donghwa Shin, Jaehyun Park, Naehyuck Chang. An energy characterization platform for memory devices and energy-aware data compression for multilevel-cell flash memory
0 -- 0Nikil D. Dutt. Editorial
0 -- 0Sabyasachi Das, Sunil P. Khatri. Resource sharing among mutually exclusive sum-of-product blocks for area reduction
0 -- 0Seongnam Kwon, Yongjoo Kim, Woo-Chul Jeun, Soonhoi Ha, Yunheung Paek. A retargetable parallel-programming framework for MPSoC
0 -- 0Tomas Pecenka, Lukás Sekanina, Zdenek Kotásek. Evolution of synthetic RTL benchmark circuits with predefined testability
0 -- 0Concepción Sanz, Manuel Prieto, José Ignacio Gómez, Antonis Papanikolaou, Miguel Miranda, Francky Catthoor. Combining system scenarios and configurable memories to tolerate unpredictability
0 -- 0Ozcan Ozturk, Mahmut T. Kandemir. ILP-Based energy minimization techniques for banked memories
0 -- 0Hiroaki Inoue, Junji Sakai, Masato Edahiro. Processor virtualization for secure mobile terminals
0 -- 0I-Lun Tseng, Adam Postula. Partitioning parameterized 45-degree polygons with constraint programming
0 -- 0Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty. Power-aware SoC test planning for effective utilization of port-scalable testers
0 -- 0Akash Kumar, Shakith Fernando, Yajun Ha, Bart Mesman, Henk Corporaal. Multiprocessor systems synthesis for multiple use-cases of multiple applications on FPGA
0 -- 0Huaizhi Wu, Martin D. F. Wong, Wilsin Gosti. Postplacement voltage assignment under performance constraints

Volume 13, Issue 2

0 -- 0Nikil Dutt. Editorial
0 -- 0James Moscola, John W. Lockwood, Young H. Cho. Reconfigurable content-based router using hardware-accelerated language parser
0 -- 0Jin-Tai Yan. Timing-driven octilinear Steiner tree construction based on Steiner-point reassignment and path reconstruction
0 -- 0Xiangrong Zhou, Peter Petrov. Heterogeneously tagged caches for low-power embedded systems with virtual memory support
0 -- 0Fang Liu, Sule Ozev, Plamen K. Nikolov. Parametric variability analysis for multistage analog circuits using analytical sensitivity modeling
0 -- 0Kishore Kumar Muchherla, Pinhong Chen, Dongsheng Ma, Janet Meiling Wang. A noniterative equivalent waveform model for timing analysis in presence of crosstalk
0 -- 0Yu Hu, Yan Lin, Lei He, Tim Tuan. Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
0 -- 0Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev. A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration
0 -- 0Alex K. Jones, Swapna R. Dontharaju, Shen Chih Tung, Leonid Mats, Peter J. Hawrylak, Raymond R. Hoare, James T. Cain, Marlin H. Mickle. Radio frequency identification prototyping
0 -- 0Anna Bernasconi, Valentina Ciriani, Roberto Cordone. The optimization of kEP-SOPs: Computational complexity, approximability and experiments
0 -- 0Nikhil Saluja, Kanupriya Gulati, Sunil P. Khatri. SAT-based ATPG using multilevel compatible don t-cares
0 -- 0R. Iris Bahar, Krishnendu Chakrabarty. Introduction to joint ACM JETC/TODAES special issue on new, emerging, and specialized technologies
0 -- 0Alexandro Baldassin, Paulo Centoducatte, Sandro Rigo, Daniel C. Casarotto, Luiz C. V. dos Santos, Max R. de O. Schultz, Olinto J. V. Furtado. An open-source binary utility generator
0 -- 0Lei Cheng, Deming Chen, Martin D. F. Wong. A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

Volume 13, Issue 1

0 -- 0Marc Boule, Zeljko Zilic. Automata-based assertion-checker synthesis of PSL properties
0 -- 0Meng-Chiou Wu, Rung-Bin Lin, Shih-Cheng Tsai. Chip placement in a reticle for multiple-project wafer fabrication
0 -- 0Chao-Wen Tzeng, Jheng-Syun Yang, Shi-Yu Huang. A versatile paradigm for scan chain diagnosis of complex faults using signal processing techniques
0 -- 0Yu-Shih Su, Po-Hsien Chang, Shih-Chieh Chang, TingTing Hwang. Synthesis of a novel timing-error detection architecture
0 -- 0Nicholas H. Zamora, Xiaoping Hu, Ümit Y. Ogras, Radu Marculescu. Enabling multimedia using resource-constrained video processing techniques: A node-centric perspective
0 -- 0Chiu-Wing Sham, Evangeline F. Y. Young, Hai Zhou. Optimizing wirelength and routability by searching alternative packings in floorplanning
0 -- 0Smita Krishnaswamy, George F. Viamontes, Igor L. Markov, John P. Hayes. Probabilistic transfer matrices in symbolic reliability analysis of logic circuits
0 -- 0Hai Zhou. A new efficient retiming algorithm derived by formal manipulation
0 -- 0Ümit Y. Ogras, Radu Marculescu. Analysis and optimization of prediction-based flow control in networks-on-chip
0 -- 0Gianpiero Cabodi, Marco Murciano, Sergio Nocco, Stefano Quer. Boosting interpolation with dynamic localized abstraction and redundancy removal
0 -- 0Xiangrong Zhou, Chenjie Yu, Alokika Dash, Peter Petrov. Application-aware snoop filtering for low-power cache coherence in embedded multiprocessors
0 -- 0Sami Taktak, Jean Lou Desbarbieux, Emmanuelle Encrenaz. A tool for automatic detection of deadlock in wormhole networks on chip
0 -- 0Ali Abbasian, Safar Hatami, Ali Afzali-Kusha, Massoud Pedram. Wavelet-based dynamic power management for nonstationary service requests
0 -- 0Kyungsoo Lee, Naehyuck Chang, Jianli Zhuo, Chaitali Chakrabarti, Sudheendra Kadri, Sarma B. K. Vrudhula. A fuel-cell-battery hybrid for portable embedded systems
0 -- 0Nikil Dutt. Editorial
0 -- 0Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen. Tailoring circuit-switched network-on-chip to application-specific system-on-chip by two optimization schemes
0 -- 0Wei Chung Chao, Wai-Kei Mak. Low-power gated and buffered clock network construction
0 -- 0Hafizur Rahaman, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir. C-testable bit parallel multipliers over ::::GF::::(2:::::::m:::::::)
0 -- 0F. Ryan Johnson, JoAnn M. Paul. Interrupt modeling for efficient high-level scheduler design space exploration
0 -- 0Michael S. Hsiao, Robert B. Jones. Introduction to special section on high-level design, validation, and test
0 -- 0Andreas Raabe, Philipp A. Hartmann, Joachim K. Anlauf. ReChannel: Describing and simulating reconfigurable hardware in systemC
0 -- 0Yongjin Ahn, Keesung Han, Ganghee Lee, Hyunjik Song, Jun-hee Yoo, Kiyoung Choi, Xingguang Feng. SoCDAL: System-on-chip design AcceLerator