| 309 | -- | 340 | Gianpiero Cabodi, Paolo Camurati, Stefano Quer. Auxiliary variables for BDD-based representation and manipulation of Boolean functions |
| 341 | -- | 388 | Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao. Bounded-skew clock and Steiner routing |
| 389 | -- | 407 | Wen-Ben Jone, K. S. Tsai. Confidence analysis for defect-level estimation of VLSI random testing |
| 408 | -- | 436 | Anmol Mathur, Ali Dasdan, Rajesh K. Gupta. Rate analysis for embedded systems |
| 437 | -- | 462 | Peichen Pan, C. L. Liu. Optimal clock period FPGA technology mapping for sequential circuits |
| 463 | -- | 486 | Michael A. Riepe, Karem A. Sakallah. The edge-based design rule model revisited |
| 487 | -- | 495 | Alan Su 0002, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee. Eliminating false loops caused by sharing in control path |
| 496 | -- | 514 | Hai Zhou, D. F. Wong. Optimal river routing with crosstalk constraints |