Journal: ACM Trans. Design Autom. Electr. Syst.

Volume 3, Issue 4

515 -- 523Claudio Passerone, Claudio Sansoè, Luciano Lavagno, Patrick C. McGeer, Jonathan Martin, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli. Modeling reactive systems in Java
524 -- 532Li-C. Wang, Magdy S. Abadir, Jing Zeng. On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays
533 -- 553Ali Dasdan, Dinesh Ramanathan, Rajesh K. Gupta. A timing-driven design and validation methodology for embedded real-time systems
554 -- 562Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee. ATM switch design by high-level modeling, formal verification and high-level synthesi
563 -- 580James K. Huggins, David Van Campenhout. Specification and verification of pipelining in the ARM2 RISC microprocessor
581 -- 599David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown. High-level design verification of microprocessors via error modeling
600 -- 625Gagan Hasteer, Anmol Mathur, Prithviraj Banerjee. Efficient equivalence checking of multi-phase designs using phase abstraction and retiming
626 -- 634Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda. EXFI: a low-cost fault injection system for embedded microprocessor-based boards

Volume 3, Issue 3

309 -- 340Gianpiero Cabodi, Paolo Camurati, Stefano Quer. Auxiliary variables for BDD-based representation and manipulation of Boolean functions
341 -- 388Jason Cong, Andrew B. Kahng, Cheng-Kok Koh, Chung-Wen Albert Tsao. Bounded-skew clock and Steiner routing
389 -- 407Wen-Ben Jone, K. S. Tsai. Confidence analysis for defect-level estimation of VLSI random testing
408 -- 436Anmol Mathur, Ali Dasdan, Rajesh K. Gupta. Rate analysis for embedded systems
437 -- 462Peichen Pan, C. L. Liu. Optimal clock period FPGA technology mapping for sequential circuits
463 -- 486Michael A. Riepe, Karem A. Sakallah. The edge-based design rule model revisited
487 -- 495Alan Su 0002, Yu-Chin Hsu, Ta-Yung Liu, Mike Tien-Chien Lee. Eliminating false loops caused by sharing in control path
496 -- 514Hai Zhou, D. F. Wong. Optimal river routing with crosstalk constraints

Volume 3, Issue 2

109 -- 135Pao-Ann Hsiung, Chung-Hwang Chen, Trong-Yen Lee, Sao-Jie Chen. ICOS: an intelligent concurrent object-oriented synthesis methodology for multiprocessor systems
136 -- 161Guido Araujo, Sharad Malik. Code generation for fixed-point DSPs
162 -- 180Giri Tiruvuri, Moon Chung. Estimation of lower bounds in scheduling algorithms for high-level synthesis
181 -- 208Frank Vahid, Thuy Dm Le, Yu-Chin Hsu. Functional partitioning improvements over structural partitioning for packaging constraints and synthesis: tool performance
209 -- 230Gernot Koch, Wolfgang Rosenstiel, Udo Kebschull. Breakpoints and breakpoint detection in source-level emulation
231 -- 248Irith Pomeranz, Sudhakar M. Reddy. Functional test generation for delay faults in combinational circuits
249 -- 271Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi. Structural diagnosis of interconnects by coloring
272 -- 284Dinesh P. Mehta. Estimating the storage requirements of the rectangular and L-shaped corner stitching data structures
285 -- 307Subhrajit Bhattacharya, Sujit Dey, Franc Brglez. Effects of resource sharing on circuit delay: an assignment algorithm for clock period optimization

Volume 3, Issue 1

1 -- 20Eric W. Johnson, Jay B. Brockman. Measurement and analysis of sequential design processes
21 -- 50Karim Khordoc, Eduard Cerny. Semantics and verification of action diagrams with linear timing
51 -- 75Stan Y. Liao, Kurt Keutzer, Steven W. K. Tjiang, Srinivas Devadas. A new viewpoint on code generation for directed acyclic graphs
76 -- 107C.-J. Richard Shi, Janusz A. Brzozowski. Cluster-cover a theoretical framework for a class of VLSI-CAD optimization problems