| 1 | -- | 13 | Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff. The CSI multimedia architecture |
| 14 | -- | 26 | Emil Talpes, Diana Marculescu. Execution cache-based microarchitecture for power-efficient superscalar processors |
| 27 | -- | 38 | Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy. A process-tolerant cache architecture for improved yield in nanoscale technologies |
| 39 | -- | 57 | George A. Constantinides, Peter Y. K. Cheung, Wayne Luk. Optimum and heuristic synthesis of multiple word-length architectures |
| 58 | -- | 74 | Dongming Peng, Mi Lu. Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations |
| 75 | -- | 85 | Yiran Chen, Kaushik Roy, Cheng-Kok Koh. Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors |
| 86 | -- | 95 | Lok-Kee Ting, Roger Woods, C. F. N. Cowan. Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers |
| 96 | -- | 105 | Herman Schmit, Vikas Chandra. Layout techniques for FPGA switch blocks |
| 106 | -- | 125 | Dongming Peng, Mi Lu. On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms |
| 126 | -- | 139 | Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli. A robust self-calibrating transmission scheme for on-chip networks |
| 140 | -- | 152 | Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici. Synchronization overhead in SOC compressed test |
| 153 | -- | 158 | Ahmad A. Hiasat. VLSI implementation of new arithmetic residue to binary decoders |
| 158 | -- | 162 | Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu. Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design |