Journal: IEEE Trans. VLSI Syst.

Volume 13, Issue 9

1013 -- 1022Fei Sun, Tong Zhang. Parallel high-throughput limited search trellis decoder VLSI design
1023 -- 1034Daehong Kim, Dongwan Shin, Kiyoung Choi. Pipelining with common operands for power-efficient linear systems
1035 -- 1047Yan Lin, Fei Li, Lei He. Circuits and architectures for field programmable gate array with configurable supply voltage
1048 -- 1059Ray C. C. Cheung, N. J. Telle, Wayne Luk, Peter Y. K. Cheung. Customizable elliptic curve cryptosystems
1060 -- 1071Xiaomeng Shi, Jianguo Ma, Kiat Seng Yeo, Manh Anh Do, Erping Li. Equivalent circuit model of on-wafer CMOS interconnects for RFICs
1072 -- 1078Yu Cao, Xiao-dong Yang, Xuejue Huang, Dennis Sylvester. Switch-factor based loop RLC modeling for efficient timing analysis
1079 -- 1086Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis. Accumulator-based test generation for robust sequential fault testing in DSP cores in near-optimal time
1087 -- 1095Irith Pomeranz, Sudhakar M. Reddy. Autoscan: a scan design without external scan inputs or outputs
1096 -- 1098Ashkan Ashrafi, Reza Adhami. Comments on A 13-bit resolution ROM-less direct digital frequency synthesizer based on a trigonometric quadruple angle formula
1098 -- 1103X. P. Yu, Manh Anh Do, Lin Jia, Jianguo Ma, Kiat Seng Yeo. Design of a low power wide-band high resolution programmable frequency divider
1103 -- 1107Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh. Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages

Volume 13, Issue 8

885 -- 898Hassan Hassan, Mohab Anis, Mohamed I. Elmasry. MOS current mode circuits: analysis, design, and variability
899 -- 910Ajay Joshi, Jeffrey A. Davis. Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI)
911 -- 920Dong-U Lee, Wayne Luk, John D. Villasenor, Guanglie Zhang, Philip Heng Wai Leong. A hardware Gaussian noise generator using the Wallace method
921 -- 933Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer. Area-efficient high-throughput MAP decoder architectures
934 -- 942Azadeh Davoodi, Ankur Srivastava. Power-driven simultaneous resource binding and floorplanning: a probabilistic approach
943 -- 956Michele Favalli. A fuzzy model for path delay fault detection
957 -- 970Rupesh S. Shelar, Sachin S. Sapatnekar. BDD decomposition for delay oriented pass transistor logic synthesis
971 -- 975Magdy A. El-Moursy, Eby G. Friedman. Exponentially tapered H-tree clock distribution networks
976 -- 979Wu Jigang, Thambipillai Srikanthan, Heiko Schröder. Efficient reconfigurable techniques for VLSI arrays with 6-port switches
979 -- 984Chunsheng Liu, Krishnendu Chakrabarty. Design and analysis of compact dictionaries for diagnosis in scan-BIST
984 -- 988T. Egan, S. Mourad. Design-for-testability for embedded delay-locked loops
989 -- 992Viktor Fischer, Milos Drutarovský, Pawel Chodowiec, F. Gramain. InvMixColumn decomposition and multilevel resource sharing in AES implementations
992 -- 996Ge Yang, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang. A 32-bit carry lookahead adder using dual-path all-N logic
996 -- 1001Maria K. Michael, Spyros Tragoudas. Function-based compact test pattern generation for path delay faults
1002 -- 1012Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa. A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*

Volume 13, Issue 7

783 -- 793G. Lakshminarayanan, B. Venkataramani. Optimization Techniques for FPGA-Based Wave-Pipelined DSP Blocks
794 -- 807Jing Huang, Mehdi Baradaran Tahoori, Fabrizio Lombardi. Fault Tolerance of Switch Blocks and Switch Block Arrays in FPGA
808 -- 818Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa. A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design
819 -- 832Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla. Global Passivity Enforcement Algorithm for Macromodels of Interconnect Subnetworks Characterized by Tabulated Data
833 -- 842P. Gui, Fouad E. Kiamilev, X. Q. Wang, M. J. MacFadden, X. L. Wang, N. Waite, M. W. Haney, C. Kuznia. A Source-Synchronous Double-Data-Rate Parallel Optical Transceiver IC
843 -- 851Ajit Sharma, P. Birrer, S. K. Arunachalam, Chenggang Xu, Terri S. Fiez, Kartikeya Mayaram. Accurate Prediction of Substrate Parasitics in Heavily Doped CMOS Processes Using a Calibrated Boundary Element Solver
852 -- 860Christopher S. Taillefer, Gordon W. Roberts. Reducing Measurement Uncertainty in a DSP-Based Mixed-Signal Test Environment Without Increasing Test Time
861 -- 864Y. S. Kwon, C. M. Kyung. ATOMi: An Algorithm for Circuit Partitioning Into Multiple FPGAs Using Time-Multiplexed, Off-Chip, Multicasting Interconnection Architecture
865 -- 868H. Ando, Nestoras Tzartzanis, William W. Walker. A Case Study: Power and Performance Improvement of a Chip Multiprocessor for Transaction Processing
869 -- 872S. Hua, G. Qu. Voltage Setup Problem for Embedded Systems With Multiple Voltages
872 -- 877Xinmiao Zhang, Keshab K. Parhi. High-Speed Architectures for Parallel Long BCH Encoders
877 -- 881Andreas Moshovos, Babak Falsafi, Farid N. Najm, Navid Azizi. A Case for Asymmetric-Cell Cache Memories

Volume 13, Issue 6

641 -- 654Atanu Chattopadhyay, Zeljko Zilic. GALDS: a complete framework for designing multiclock ASICs and SoCs
655 -- 667Srinivasa R. Sridhara, Naresh R. Shanbhag. Coding for system-on-chip networks: a unified framework
668 -- 677Yangdong Deng, W. P. Maly. 2.5-dimensional VLSI system integration
678 -- 685Qiang Xu, Nicola Nicolici. Wrapper design for multifrequency IP cores
686 -- 695Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits
696 -- 707Haris Lekatsas, Jörg Henkel, Wayne Wolf. Approximate arithmetic coding for bus transition reduction in low power designs
708 -- 718J. Chien-Mo Li. Diagnosis of single stuck-at faults and multiple timing faults in scan chains
719 -- 731Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty. Nine-coded compression technique for testing embedded cores in SoCs
732 -- 741Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang. Design-for-testability and fault-tolerant techniques for FFT processors
742 -- 745Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu. A built-in self-repair design for RAMs with 2-D redundancy
745 -- 750Anh Dinh, Xiao Hu. A hardware-efficient technique to implement a trellis code modulation decoder
750 -- 754Rishi Chaturvedi, Jiang Hu. An efficient merging scheme for prescribed skew clock routing
754 -- 758Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy. Comparison of high-performance VLSI adders in the energy-delay space
758 -- 762S. W. Oldridge, Steven J. E. Wilton. A novel FPGA architecture supporting wide, shallow memories
762 -- 765Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava. Simultaneous V/sub t/ selection and assignment for leakage optimization
765 -- 769Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller. Synthesis of Fredkin-Toffoli reversible networks

Volume 13, Issue 5

513 -- 524Kamal S. Khouri, Ganesh Lakshminarayana, Niraj K. Jha. Memory binding for performance optimization of control-flow intensive behavioral descriptions
525 -- 538Nattawut Thepayasuwan, Alex Doboli. Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed
539 -- 552Sungchan Kim, Chaeseok Im, Soonhoi Ha. Schedule-aware performance estimation of communication architecture for efficient design space exploration
553 -- 563Fred Ma, John P. Knight, Calvin Plett. Physical resource binding for a coarse-grain reconfigurable array using evolutionary algorithms
564 -- 576Hai Li, Chen-Yong Cher, Kaushik Roy, T. N. Vijaykumar. Combined circuit and architectural level variable supply-voltage scaling for low power
577 -- 590Nikola Nedovic, Vojin G. Oklobdzija. Dual-edge triggered storage elements and clocking strategy for low-power systems
591 -- 603Emil Talpes, Diana Marculescu. Toward a multiple clock/voltage island design style for power-aware processors
604 -- 617Ted H. Szymanski, Honglin Wu, Amir Gourgy. Power complexity of multiplexer-based optoelectronic crossbar switches
618 -- 629Amin Q. Safarian, Ahmad Yazdi, Payam Heydari. Design and analysis of an ultrawide-band distributed CMOS mixer
630 -- 638Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti. A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control

Volume 13, Issue 4

413 -- 426Xinmiao Zhang, Keshab K. Parhi. Fast factorization architecture in soft-decision Reed-Solomon decoding
427 -- 438Rostislav (Reuven) Dobkin, Michael Peleg, Ran Ginosar. Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders
439 -- 447Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen. VLSI architectural design tradeoffs for sliding-window log-MAP decoders
448 -- 461Sunan Tugsinavisut, Youpyo Hong, Daewook Kim, Kyeounsoo Kim, Peter A. Beerel. Efficient asynchronous bundled-data pipelines for DCT matrix-vector multiplication
462 -- 475M. E. Litvin, S. Mourad. Self-reset logic for fast arithmetic applications
476 -- 483Chang Hoon Kim, Chun-Pyo Hong, Soonhak Kwon. A digit-serial multiplier for finite field GF(2/sup m/)
484 -- 488Russell Tessier, Sriram Swaminathan, Ramaswamy Ramaswamy, Dennis Goeckel, Wayne P. Burleson. A reconfigurable, power-efficient adaptive Viterbi decoder
489 -- 493Keshab K. Parhi. Design of multigigabit multiplexer-loop-based decision feedback equalizers
494 -- 498M. Tiwari, Yuming Zhu, C. Chakrabarti. Memory sub-banking scheme for high throughput MAP-based SISO decoders
498 -- 502Sri Parameswaran, Jörg Henkel. Instruction code mapping for performance increase and energy reduction in embedded computer systems
503 -- 507Swarup Bhunia, Kaushik Roy. A novel wavelet transform-based transient current analysis for fault detection and localization

Volume 13, Issue 3

297 -- 307Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry. POMR: a power-aware interconnect optimization methodology
308 -- 318. Optimization of throughput performance for low-power VLSI interconnects
319 -- 329Jinjun Xiong, Lei He. Extended global routing with RLC crosstalk constraints
330 -- 338Husni M. Habal, Kartikeya Mayaram, Terri S. Fiez. Accurate and efficient simulation of synchronous digital switching noise in systems on a chip
339 -- 348T. Chen. On the impact of on-chip inductance on signal nets under the influence of power grid noise
349 -- 357Chris H. Kim, Jae-Joon Kim, Saibal Mukhopadhyay, Kaushik Roy. A forward body-biased low-leakage SRAM cache: device, circuit and architecture considerations
358 -- 369John C. Koob, Daniel A. Leder, Raymond J. Sung, Tyler L. Brandon, Duncan G. Elliott, Bruce F. Cockburn, L. McIlrath. Design of a 3-D fully depleted SOI computational RAM
370 -- 383Sanghyeon Baeg, Sung Soo Chung. Analytical test buffer design for differential signaling I/O buffers by error syndrome analysis
384 -- 395Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy. Low-power scan design using first-level supply gating
396 -- 400Magdy A. El-Moursy, Eby G. Friedman. Shielding effect of on-chip interconnect inductance
401 -- 405Mohamed A. Elgamel, Ashok Kumar, Magdy A. Bayoumi. Efficient shield insertion for inductive noise reduction in nanometer technologies
405 -- 408Chua-Chin Wang, Yih-Long Tseng, Chih-Chiang Chiu. A temperature-insensitive self-recharging circuitry used in DRAMs

Volume 13, Issue 2

169 -- 180Brian Moore, Martin Margala, Christopher J. Backhouse. Design of wireless on-wafer submicron characterization system
181 -- 190Marko Kosunen, Jouko Vankka, Mikko Waltari, Kari Halonen. A multicarrier QAM modulator for WCDMA base-station with on-chip D/A converter
191 -- 200Francesco Centurelli, A. Golfarelli, J. Guinea, L. Masini, D. Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti. A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability
201 -- 210Liming Xiu, Zhihong You. A Flying-Adder frequency synthesis architecture of reducing VCO stages
211 -- 225Vijay Raghunathan, Cristiano Pereira, Mani B. Srivastava, Rajesh K. Gupta. Energy-aware wireless systems with adaptive power-fidelity tradeoffs
226 -- 237P. Chowdhury, C. Chakrabarti. Static task-scheduling algorithms for battery-powered DVS systems
238 -- 254W. W. Bachmann, Sorin A. Huss. Efficient algorithms for multilevel power estimation of VLSI circuits
255 -- 265Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang. A micropower low-voltage multiplier with reduced spurious switching
266 -- 277Neil Burgess. Prenormalization rounding in IEEE floating-point operations using a flagged prefix adder
278 -- 287Soha Hassoun, Murali Kudlugi, Duaine Pryor, Charles Selvidge. A transaction-based unified architecture for simulation and emulation
288 -- 292Jai-Ming Lin, Yao-Wen Chang. TCG: A transitive closure graph-based representation for general floorplans

Volume 13, Issue 12

1329 -- 1339Shrirang K. Karandikar, Sachin S. Sapatnekar. Fast comparisons of circuit implementations
1340 -- 1348Chuan Lin, Hai Zhou. Wire retiming as fixpoint computation
1349 -- 1361Sandy Irani, Gaurav Singh, Sandeep K. Shukla, Rajesh K. Gupta. An overview of the competitive and adversarial approaches to designing dynamic power management strategies
1362 -- 1375Anup Kumar Sultania, Dennis Sylvester, Sachin S. Sapatnekar. Gate oxide leakage and delay tradeoffs for dual-T/sub ox/ circuits
1376 -- 1383Rajeev R. Rao, Harmander Deogun, David Blaauw, Dennis Sylvester. Bus encoding for total power reduction using a leakage-aware buffer configuration
1384 -- 1393Aristides Efthymiou, John Bainbridge, Douglas A. Edwards. Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
1394 -- 1398Andreas Dandalis, Viktor K. Prasanna. Configuration compression for FPGA-based embedded systems
1399 -- 1402Chua-Chin Wang, Tzung-Je Lee, Yu-Tzu Hsiao, U. Fat Chio, Chi-Chun Huang, J.-J. J. Chin, Ya-Hsin Hsueh. A multiparameter implantable microstimulator SOC

Volume 13, Issue 11

1213 -- 1224Arijit Raychowdhury, Bipul Chandra Paul, Swarup Bhunia, Kaushik Roy. Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation
1225 -- 1238Himanshu Kaul, Dennis Sylvester, Mark Anders, Ram Krishnamurthy. Design and analysis of spatial encoding circuits for peak power reduction in on-chip buses
1239 -- 1252Bo Zhai, David T. Blaauw, Dennis Sylvester, Krisztián Flautner. The limit of dynamic voltage scaling and insomniac dynamic voltage scaling
1253 -- 1265Robert B. Staszewski, Roman Staszewski, John L. Wallberg, Tom Jung, Chih-Ming Hung, Jinseok Koh, Dirk Leipold, K. Maggio, Poras T. Balsara. SoC with an integrated DSP and a 2.4-GHz RF transmitter
1266 -- 1274Antonio G. M. Strollo, Davide De Caro, E. Napoli, Nicola Petra. A novel high-speed sense-amplifier-based flip-flop
1275 -- 1285Qiang Xu, Nicola Nicolici. Modular and rapid testing of SOCs with unwrapped logic blocks
1286 -- 1295Qikai Chen, Hamid Mahmoodi-Meimand, Swarup Bhunia, Kaushik Roy. Efficient testing of SRAM with optimized march sequences and a novel DFT technique for emerging failures due to process variations
1296 -- 1304Bhaskar Chatterjee, Manoj Sachdev. Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
1305 -- 1319Ju-wook Jang, Seonil B. Choi, Viktor K. Prasanna. Energy- and time-efficient matrix multiplication on FPGAs
1320 -- 1324Peter Hallschmid, Steven J. E. Wilton. Routing architecture optimizations for high-density embedded programmable IP cores
1324 -- 1328Weiping Liao, Joseph M. Basile, Lei He. Microarchitecture-level leakage reduction with data retention

Volume 13, Issue 10

1113 -- 1126Noureddine Chabini, Wayne Wolf. Unification of scheduling, binding, and retiming to reduce power consumption under timings and resources constraints
1127 -- 1135Hua Wang, Miguel Miranda, Antonis Papanikolaou, Francky Catthoor, Wim Dehaene. Variable tapered pareto buffer design and implementation allowing run-time configuration for low-power embedded SRAMs
1136 -- 1146Mahmut T. Kandemir, Mary Jane Irwin, Guangyu Chen, Ibrahim Kolcu. Compiler-guided leakage optimization for banked scratch-pad memories
1147 -- 1156Nam Sung Kim, David Blaauw, Trevor N. Mudge. Quantitative analysis and optimization techniques for on-chip cache leakage power
1157 -- 1166Vijay Degalahal, Lin Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. Soft errors issues in low-power caches
1167 -- 1178Seungbae Lee, Gi-Joon Nam, Junseok Chae, Hanseup Kim, Alan J. Drake. Two-dimensional position detection system with MEMS accelerometers, readout circuitry, and microprocessor for padless mouse applications
1179 -- 1189Zachary K. Baker, Viktor K. Prasanna. A computationally efficient engine for flexible intrusion detection
1190 -- 1199Russell Tessier, David Jasinski, Atul Maheshwari, Aiyappan Natarajan, Weifeng Xu, Wayne P. Burleson. An energy-aware active smart card
1200 -- 1205Daihyun Lim, Jae W. Lee, Blaise Gassend, G. Edward Suh, Marten van Dijk, Srinivas Devadas. Extracting secret keys from integrated circuits
1205 -- 1209Y. Abulafia, Avner Kornfeld. Estimation of FMAX and ISB in microprocessors

Volume 13, Issue 1

1 -- 13Dmitry Cheresiz, Ben H. H. Juurlink, Stamatis Vassiliadis, Harry A. G. Wijshoff. The CSI multimedia architecture
14 -- 26Emil Talpes, Diana Marculescu. Execution cache-based microarchitecture for power-efficient superscalar processors
27 -- 38Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy. A process-tolerant cache architecture for improved yield in nanoscale technologies
39 -- 57George A. Constantinides, Peter Y. K. Cheung, Wayne Luk. Optimum and heuristic synthesis of multiple word-length architectures
58 -- 74Dongming Peng, Mi Lu. Non-RAM-based architectural designs of wavelet-based digital systems based on novel nonlinear I/O data space transformations
75 -- 85Yiran Chen, Kaushik Roy, Cheng-Kok Koh. Current demand balancing: a technique for minimization of current surge in high performance clock-gated microprocessors
86 -- 95Lok-Kee Ting, Roger Woods, C. F. N. Cowan. Virtex FPGA implementation of a pipelined adaptive LMS predictor for electronic support measures receivers
96 -- 105Herman Schmit, Vikas Chandra. Layout techniques for FPGA switch blocks
106 -- 125Dongming Peng, Mi Lu. On exploring inter-iteration parallelism within rate-balanced multirate multidimensional DSP algorithms
126 -- 139Frederic Worm, Paolo Ienne, Patrick Thiran, Giovanni De Micheli. A robust self-calibrating transmission scheme for on-chip networks
140 -- 152Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici. Synchronization overhead in SOC compressed test
153 -- 158Ahmad A. Hiasat. VLSI implementation of new arithmetic residue to binary decoders
158 -- 162Yu Cao, Xuejue Huang, Dennis Sylvester, Tsu-Jae King, Chenming Hu. Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design