641 | -- | 654 | Atanu Chattopadhyay, Zeljko Zilic. GALDS: a complete framework for designing multiclock ASICs and SoCs |
655 | -- | 667 | Srinivasa R. Sridhara, Naresh R. Shanbhag. Coding for system-on-chip networks: a unified framework |
668 | -- | 677 | Yangdong Deng, W. P. Maly. 2.5-dimensional VLSI system integration |
678 | -- | 685 | Qiang Xu, Nicola Nicolici. Wrapper design for multifrequency IP cores |
686 | -- | 695 | Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang. A review of 0.18-/spl mu/m full adder performances for tree structured arithmetic circuits |
696 | -- | 707 | Haris Lekatsas, Jörg Henkel, Wayne Wolf. Approximate arithmetic coding for bus transition reduction in low power designs |
708 | -- | 718 | J. Chien-Mo Li. Diagnosis of single stuck-at faults and multiple timing faults in scan chains |
719 | -- | 731 | Mohammad Tehranipoor, Mehrdad Nourani, Krishnendu Chakrabarty. Nine-coded compression technique for testing embedded cores in SoCs |
732 | -- | 741 | Shyue-Kung Lu, Jen-Sheng Shih, Shih-Chang Huang. Design-for-testability and fault-tolerant techniques for FFT processors |
742 | -- | 745 | Jin-Fu Li, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu. A built-in self-repair design for RAMs with 2-D redundancy |
745 | -- | 750 | Anh Dinh, Xiao Hu. A hardware-efficient technique to implement a trellis code modulation decoder |
750 | -- | 754 | Rishi Chaturvedi, Jiang Hu. An efficient merging scheme for prescribed skew clock routing |
754 | -- | 758 | Vojin G. Oklobdzija, Bart R. Zeydel, Hoang Q. Dao, Sanu Mathew, Ram Krishnamurthy. Comparison of high-performance VLSI adders in the energy-delay space |
758 | -- | 762 | S. W. Oldridge, Steven J. E. Wilton. A novel FPGA architecture supporting wide, shallow memories |
762 | -- | 765 | Vishal Khandelwal, Azadeh Davoodi, Ankur Srivastava. Simultaneous V/sub t/ selection and assignment for leakage optimization |
765 | -- | 769 | Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller. Synthesis of Fredkin-Toffoli reversible networks |