| 273 | -- | 291 | Chien-In Henry Chen, Joel T. Yuen. Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design |
| 304 | -- | 311 | Alex Orailoglu, Ramesh Karri. Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures |
| 312 | -- | 319 | Ming-Bo Lin, A. Yavuz Oruç. A fault-tolerant permutation network modulo arithmetic processor |
| 320 | -- | 332 | Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj. Logic design error diagnosis and correction |
| 333 | -- | 342 | Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang. Certified timing verification and the transition delay of a logic circuit |
| 343 | -- | 353 | P. G. Tzionas, Panagiotis G. Tsalides, Adonios Thanailakis. A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation |
| 354 | -- | 357 | R. V. Pelletier, Robert D. McLeod. Loop based design for wafer scale systems |
| 357 | -- | 360 | Chang N. Zhang, J. H. Weston, Y.-F. Yan. Determining objective functions in systolic array designs |
| 360 | -- | 364 | K. Tsang, Belle W. Y. Wei. A VLSI architecture for a real-time code book generator and encoder of a vector quantizer |
| 365 | -- | 367 | Barry S. Fagin, C. Renard. Field programmable gate arrays and floating point arithmetic |
| 368 | -- | 372 | Jacob Savir, Srinivas Patil. On broad-side delay test |
| 372 | -- | 377 | Alexandre Yakovlev, A. Petrov, Luciano Lavagno. A low latency asynchronous arbitration circuit |
| 377 | -- | 381 | Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin. Power-delay characteristics of CMOS adders |