External Links

    Journal: IEEE Trans. VLSI Syst.

    Volume 2, Issue 4

    391 -- 397Lars Skovby Nielsen, C. Niessen, Jens Sparsø, Kees van Berkel. Low-power operation using self-timed circuits and adaptive scaling of the supply voltage
    398 -- 407William C. Athas, Lars J. Svensson, J. G. Koller, Nestoras Tzartzanis, E. Ying-Chin Chou. Low-power digital systems based on adiabatic-switching principles
    408 -- 425Jason Cong, Cheng-Kok Koh. Simultaneous driver and wire sizing for performance and power optimization
    426 -- 436Mazhar Alidina, José C. Monteiro, Srinivas Devadas, Abhijit Ghosh, Marios C. Papaefthymiou. Precomputation-based sequential logic optimization for low power
    437 -- 445Vivek Tiwari, Sharad Malik, Andrew Wolfe. Power analysis of embedded software: a first step towards software power minimization
    446 -- 455Farid N. Najm. A survey of power estimation techniques in VLSI circuits
    456 -- 471Samit Chaudhuri, Robert A. Walker, J. E. Mitchell. Analyzing and exploiting the structure of the constraints in the ILP approach to the scheduling problem
    472 -- 488Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi. A C-testable carry-free divider
    489 -- 501Eric Q. Kang, Rung-Bin Lin, Eugene Shragowitz. Fuzzy logic approach to VLSI placement
    502 -- 507Chaitali Chakrabarti, Li-Yu Wang. Novel sorting network-based architectures for rank order filters
    508 -- 511Kaushik Roy, Sudip Nag. Automatic synthesis of FPGA channel architecture for routability and performance
    512 -- 516S. Kundu. Diagnosing scan chain faults
    516 -- 521Charles E. Stroud. Reliability of majority voting based VLSI fault-tolerant circuits
    522 -- 524R. Katti. A modified Booth algorithm for high radix fixed-point multiplication

    Volume 2, Issue 3

    273 -- 291Chien-In Henry Chen, Joel T. Yuen. Automated synthesis of pseudo-exhaustive test generator in VLSI BIST design
    304 -- 311Alex Orailoglu, Ramesh Karri. Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures
    312 -- 319Ming-Bo Lin, A. Yavuz Oruç. A fault-tolerant permutation network modulo arithmetic processor
    320 -- 332Pi-Yu Chung, Yi-Min Wang, Ibrahim N. Hajj. Logic design error diagnosis and correction
    333 -- 342Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert Wang. Certified timing verification and the transition delay of a logic circuit
    343 -- 353P. G. Tzionas, Panagiotis G. Tsalides, Adonios Thanailakis. A new, cellular automaton-based, nearest neighbor pattern classifier and its VLSI implementation
    354 -- 357R. V. Pelletier, Robert D. McLeod. Loop based design for wafer scale systems
    357 -- 360Chang N. Zhang, J. H. Weston, Y.-F. Yan. Determining objective functions in systolic array designs
    360 -- 364K. Tsang, Belle W. Y. Wei. A VLSI architecture for a real-time code book generator and encoder of a vector quantizer
    365 -- 367Barry S. Fagin, C. Renard. Field programmable gate arrays and floating point arithmetic
    368 -- 372Jacob Savir, Srinivas Patil. On broad-side delay test
    372 -- 377Alexandre Yakovlev, A. Petrov, Luciano Lavagno. A low latency asynchronous arbitration circuit
    377 -- 381Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin. Power-delay characteristics of CMOS adders

    Volume 2, Issue 2

    137 -- 148Jason Cong, Yuzheng Ding. On area/depth trade-off in LUT-based FPGA technology mapping
    149 -- 156Tassos Markas, Mark Royals, Nick Kanopoulos. Design and DCVS implementation of a self-checking bus-monitor unit for highly reliable fault-tolerant system configurations
    157 -- 171Massimo Bombana, Giacomo Buonanno, Patrizia Cavalloro, Fabrizio Ferrandi, Donatella Sciuto, Giuseppe Zaza. ALADIN: a multilevel testability analyzer for VLSI system design
    172 -- 185Andrew Seawright, Forrest Brewer. Clairvoyant: a synthesis system for production-based specification
    186 -- 195K. De, C. Natarajan, D. Nair, P. Banerjee. RSYN: a system for automated synthesis of reliable multilevel circuits
    196 -- 210S. C. Leung, Hon F. Li. A syntax-directed translation for the synthesis of delay-insensitive circuits
    211 -- 225Minjoong Rim, Ashutosh Mujumdar, Rajiv Jain, Renato De Leone. Optimal and heuristic algorithms for solving the binding problem
    226 -- 240Lishing Liu. Partial address directory for cache access
    241 -- 248Marc E. Levitt, Kaushik Roy, Jacob A. Abraham. BiCMOS logic testing
    249 -- 256Israel Koren, Zahava Koren, Charles H. Stapper. A statistical study of defect maps of large area VLSI IC s
    257 -- 260Choong Gun Oh, Hee Yong Youn. On concurrent error location and correction of FFT networks
    261 -- 265Razak Hossain, Leszek D. Wronski, Alexander Albicki. Low power design using double edge triggered flip-flops
    265 -- 270Mohammad Hossain Heydari, Ioannis G. Tollis, Chunliang Xia. Algorithms and bounds for layer assignment of MCM routing

    Volume 2, Issue 1

    1 -- 10Daniel Audet, Yvon Savaria, N. Arel. Pipelining communications in large VLSI/ULSI systems
    11 -- 20Catherine H. Gebotys. An optimization approach to the synthesis of multichip architectures
    21 -- 32Yunn Yen Chen, Yu-Chin Hsu, Chung-Ta King. MULTIPAR: behavioral partition for synthesizing multiprocessor architectures
    33 -- 44Wai-Chi Fang, Chi-Yung Chang, Bing J. Sheu, Oscal T.-C. Chen, J. C. Curlander. VLSI systolic binary tree-searched vector quantizer for image compression
    45 -- 53Chingwei Yeh, Lung-Tien Liu, Chung-Kuan Cheng, T. C. Hu, S. Ahmed, M. Liddel. Block-oriented programmable design with switching network interconnect
    54 -- 67J. Ghosh, A. Varma, N. Krishnamurthy. Distributed control schemes for fast arbitration in large crossbar networks
    68 -- 80Steve C.-Y. Huang, Wayne Wolf. Performance-driven synthesis in controller-datapath systems
    81 -- 88Lih-Gwo Jeng, Liang-Gee Chen. Rate-optimal DSP synthesis by pipeline and minimum unfolding
    89 -- 99Sungho Kang, Stephen A. Szygenda. The simulation automation system (SAS); concepts, implementation, and results
    100 -- 114Brian S. Cherkauer, Eby G. Friedman. Channel width tapering of serially connected MOSFET s with emphasis on power dissipation
    115 -- 123Neil J. Howard, Andrew M. Tyrrell, Nigel M. Allinson. The yield enhancement of field-programmable gate arrays
    124 -- 128Vojin G. Oklobdzija. An algorithmic and novel design of a leading zero detector circuit: comparison with logic synthesis
    129 -- 133Joongho Choi, Bing J. Sheu, Josephine C.-F. Chang. A Gaussian synapse circuit for analog VLSI neural networks
    runs on