| 1613 | -- | 1625 | Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li 0001. PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM |
| 1626 | -- | 1635 | Duckhwan Kim, Saibal Mukhopadhyay. Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation |
| 1636 | -- | 1648 | Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim. Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs |
| 1649 | -- | 1662 | Xianmin Chen, Niraj K. Jha. A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation |
| 1663 | -- | 1674 | Viveka Konandur Rajanna, Bharadwaj Amrutur. A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs |
| 1675 | -- | 1687 | Szu-Pang Mu, Mango C.-T. Chao, Shi-Hao Chen, Yi-Ming Wang. Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators |
| 1688 | -- | 1701 | Yang Lin, Mark Zwolinski, Basel Halak. A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors |
| 1702 | -- | 1714 | Mehdi Sadi, Mark Tehranipoor. Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs |
| 1715 | -- | 1727 | Xiaoxiao Wang, Dongrong Zhang, Donglin Su, LeRoy Winemberg, Mark Tehranipoor. A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits |
| 1728 | -- | 1738 | Hsuan-Yu Chang, Ching-Yuan Yang. A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs |
| 1739 | -- | 1748 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents |
| 1749 | -- | 1760 | Debao Wei, Libao Deng, Liyan Qiao, Peng Zhang, Xiyuan Peng. PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash |
| 1761 | -- | 1769 | Chua-Chin Wang, Deng-Shian Wang, Chiang-Hsiang Liao, Sih-Yu Chen. A Leakage Compensation Design for Low Supply Voltage SRAM |
| 1770 | -- | 1782 | Yebin Lee, Soontae Kim. CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System |
| 1783 | -- | 1793 | Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. Self-Timed Read and Write Operations in STT-MRAM |
| 1794 | -- | 1807 | Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda. Area-Aware Cache Update Trackers for Postsilicon Validation |
| 1808 | -- | 1820 | Ming-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo, Fu-Hsin Chen. Reducing Data Migration Overheads of Flash Wear Leveling in a Progressive Way |
| 1821 | -- | 1834 | Ehsan Nasiri, Javeed Shaikh, André Hahn Pereira, Vaughn Betz. Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs |
| 1835 | -- | 1848 | Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang. A Systematic Design Methodology of Asynchronous SAR ADCs |
| 1849 | -- | 1857 | Zeinab Torabi, Ghassem Jaberipur. Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range |
| 1858 | -- | 1870 | Greg Leung, Shaodi Wang, Andrew Pan, Puneet Gupta, Chi On Chui. An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits |
| 1871 | -- | 1884 | Chih-Hung Chou, Ta-Wen Kuan, Shovan Barma, Bo-Wei Chen, Wen Ji, Chih-Hsiang Peng, Jhing-Fa Wang. A New Binary-Halved Clustering Method and ERT Processor for ASSR System |
| 1885 | -- | 1894 | Kejie Huang, Rong Zhao, Yong Lian. Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs |
| 1895 | -- | 1908 | Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei. Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures |
| 1909 | -- | 1916 | Payam Masoumi Farahabadi, Kambiz K. Moez. A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS |
| 1917 | -- | 1925 | Fanyi Meng, Kaixue Ma, Kiat Seng Yeo, Shanshan Xu. 2 5-bit Passive Phase Shifter in 65-nm CMOS |
| 1926 | -- | 1935 | Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel. LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter |
| 1936 | -- | 1949 | Pascal A. Hager, Andrea Bartolini, Luca Benini. Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second |
| 1950 | -- | 1961 | Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls. High-Performance NB-LDPC Decoder With Reduction of Message Exchange |
| 1962 | -- | 1974 | Nourhan Bayasi, Temesghen Tekeste, Hani H. Saleh, Baker Mohammad, Ahsan H. Khandoker, Mohammed Ismail. Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia |
| 1975 | -- | 1983 | Immanuel Raja, Gaurab Banerjee, Mohamad A. Zeidan, Jacob A. Abraham. A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS |
| 1984 | -- | 1992 | Yung-Hsiang Ho, Chia-Yu Yao. A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation |
| 1993 | -- | 1997 | Chung-Hsien Chang, Shi-Huang Chen, Bo-Wei Chen, Wen Ji, K. Bharanitharan, Jhing-Fa Wang. Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing |
| 1998 | -- | 2002 | Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei. Trigger-Centric Loop Mapping on CGRAs |
| 2003 | -- | 2007 | Amit Chhabra, Yagnesh Dineshbhai Vaderiya. Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM |
| 2008 | -- | 2012 | Abhishek Ambede, A. Prasad Vinod. Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order |