Journal: IEEE Trans. VLSI Syst.

Volume 24, Issue 9

2813 -- 2826Bo Yuan, Bin Li, Huanhuan Chen, Xin Yao. Defect- and Variation-Tolerant Logic Mapping in Nanocrossbar Using Bipartite Matching and Memetic Algorithm
2827 -- 2836Chaudhry Adnan Aslam, Yong Liang Guan, Kui Cai. Detector for MLC NAND Flash Memory Using Neighbor-A-Priori Information
2837 -- 2850Xian Li, Karthi Duraisamy, Paul Bogdan, Turbo Majumder, Partha Pratim Pande. Network-on-Chip-Enabled Multicore Platforms for Parallel Model Predictive Control
2851 -- 2860Sara Choi, Taehui Na, Jisu Kim, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung. Corner-Aware Dynamic Gate Voltage Scheme to Achieve High Read Yield in STT-RAM
2861 -- 2872Kejie Huang, Rong Zhao. Magnetic Domain-Wall Racetrack Memory-Based Nonvolatile Logic for Low-Power Computing and Fast Run-Time-Reconfiguration
2873 -- 2886Niranjan Kulkarni, Jinghua Yang, Jae-sun Seo, Sarma B. K. Vrudhula. Reducing Power, Leakage, and Area of Standard-Cell ASICs Using Threshold Logic Flip-Flops
2887 -- 2898Vishal Khatri, Gaurab Banerjee. A 0.25-3.25-GHz Wideband CMOS-RF Spectrum Sensor for Narrowband Energy Detection
2899 -- 2910Andrew Nicholson, Artemij Iberzanov, Julian Jenkins, Tara Julia Hamilton, Torsten Lehmann. A Statistical Design Approach for a Digitally Programmable Mismatch-Tolerant High-Speed Nauta Structure Differential OTA in 65-nm CMOS
2911 -- 2917Ayman Ismail, Islam Mostafa. A Process-Tolerant, Low-Voltage, Inverter-Based OTA for Continuous-Time Σ-Δ ADC
2918 -- 2931Shyam Kumar Devarakond, Shreyas Sen, Aritra Banerjee, Abhijit Chatterjee. Digitally Assisted Built-In Tuning Using Hamming Distance Proportional Signatures in RF Circuits
2932 -- 2945Esther P. Adeva, Gerhard P. Fettweis. Efficient Architecture for Soft-Input Soft-Output Sphere Detection With Perfect Node Enumeration
2946 -- 2959Jeyavijayan J. V. Rajendran, Ozgur Sinanoglu, Ramesh Karri. Building Trustworthy Systems Using Untrusted Components: A High-Level Synthesis Approach
2960 -- 2969Erhan Ozalevli. A Compact One-Pin Mode Transition Circuit for Clock Synchronization in Current-Mode- Controlled Switching Regulators
2970 -- 2982Jorge Zarate-Roldan, Mengde Wang, Joselyn Torres, Edgar Sánchez-Sinencio. A Capacitor-Less LDO With High-Frequency PSR Suitable for a Wide Range of On-Chip Capacitive Loads
2983 -- 2992Yuh-Shyan Hwang, Jiann-Jong Chen, Wei-Jhih Hou, Pao-Hua Liao, Yi-Tsen Ku. s Transient Recovery Time Low-EMI DC-DC Buck Converter With Δ - Δ Modulator
2993 -- 2997Taehui Na, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung. Multiple-Cell Reference Scheme for Narrow Reference Resistance Distribution in Deep Submicrometer STT-RAM
2998 -- 3002Da-Wei Chang, Wei-Cheng Lin, Hsin-Hung Chen. FastRead: Improving Read Performance for Multilevel-Cell Flash Memory
3003 -- 3007Mario Garrido, Rikard Andersson, Fahad Qureshi, Oscar Gustafsson. Multiplierless Unity-Gain SDF FFTs
3008 -- 3012Zhuo Qian, Martin Margala. Low-Power Split-Radix FFT Processors Using Radix-2 Butterfly Units

Volume 24, Issue 8

2613 -- 0Krishnendu Chakrabarty, Massimo Alioto. Editorial First TVLSI Best AE and Reviewer Awards
2614 -- 2621V. Mohammed Zackriya, Harish M. Kittur. Precharge-Free, Low-Power Content-Addressable Memory
2622 -- 2633Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish. A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications
2634 -- 2642Sayeed Ahmad, Mohit Kumar Gupta, Naushad Alam, Mohd. Hasan. Single-Ended Schmitt-Trigger-Based Robust Low-Power SRAM Cell
2643 -- 2653Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls. Reduced-Complexity Nonbinary LDPC Decoder for High-Order Galois Fields Based on Trellis Min-Max Algorithm
2654 -- 2664Hongbin Sun, Wenzhe Zhao, Minjie Lv, Guiqiang Dong, Nanning Zheng, Tong Zhang 0002. Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device
2665 -- 2678Sharad Sinha, Wei Zhang. Low-Power FPGA Design Using Memoization-Based Approximate Computing
2679 -- 2688Himanshu Markandeya, Kaushik Roy 0001. Low-Power System for Detection of Symptomatic Patterns in Audio Biological Signals
2689 -- 2702Yang Xiao, Siddharth Advani, Donghwa Shin, Naehyuck Chang, Jack Sampson, Vijaykrishnan Narayanan. A Saliency-Driven LCD Power Management System
2703 -- 2711Myat Thu Linn Aung, Teck Heng Lim, Takefumi Yoshikawa, Tony Tae-Hyoung Kim. 2.31-Gb/s/ch Area-Efficient Crosstalk Canceled Hybrid Capacitive Coupling Interconnect for 3-D Integration
2712 -- 2725Chang-Chih Chen, Taizhi Liu, Linda Milor. System-Level Modeling of Microprocessor Reliability Degradation Due to Bias Temperature Instability and Hot Carrier Injection
2726 -- 2734Shyue-Kung Lu, Cheng-Ju Tsai, Masaki Hashizume. Enhanced Built-In Self-Repair Techniques for Improving Fabrication Yield and Reliability of Embedded Memories
2735 -- 2744Daniele Rossi, Vasileios Tenentes, Sheng Yang, S. Saqib Khursheed, Bashir M. Al-Hashimi. Reliable Power Gating With NBTI Aging Benefits
2745 -- 2758Amit Kumar Singh, Muhammad Shafique, Akash Kumar 0001, Jörg Henkel. Analysis and Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3-D Multicore Processors
2759 -- 2767Irith Pomeranz. A Test Selection Procedure for Improving the Accuracy of Defect Diagnosis
2768 -- 2777Junyoung Song, Sewook Hwang, Chulwoo Kim. A 4×5-Gb/s 1.12-µs Locking Time Reference-Less Receiver With Asynchronous Sampling-Based Frequency Acquisition and Clock Shared Subchannels
2778 -- 2786Boris Vaisband, Eby G. Friedman. Noise Coupling Models in Heterogeneous 3-D ICs
2787 -- 2798Alp Arslan Bayrakci. Accelerated Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling
2799 -- 2802Hyeon Uk Sim, Atul Rahman, Jongeun Lee. Efficient High-Level Synthesis for Nested Loops of Nonrectangular Iteration Spaces
2803 -- 2807Paramjeet Singh Sahni, Suresh Chandra Joshi, Nitin Gupta, Gangaikondan Subramani Visweswaran. An Equalizer With Controllable Transfer Function for 6-Gb/s HDMI and 5.4-Gb/s DisplayPort Receivers in 28-nm UTBB-FDSOI
2808 -- 2812Lei Qiu, Kai Tang, Yuanjin Zheng, Liter Siek. A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs

Volume 24, Issue 7

2413 -- 2425Chiou-Yng Lee, Pramod Kumar Meher, Chung-Hsin Liu. Area-Delay Efficient Digit-Serial Multiplier Based on k-Partitioning Scheme Combined With TMVP Block Recombination Approach
2426 -- 2437Mohammad Salehi, Mohammad Khavari Tavana, Semeen Rehman, Muhammad Shafique, Alireza Ejlali, Jörg Henkel. Two-State Checkpointing for Energy-Efficient Fault Tolerance in Hard Real-Time Systems
2438 -- 2448Andres F. Gomez, Víctor H. Champac. Early Selection of Critical Paths for Reliable NBTI Aging-Delay Monitoring
2449 -- 2461Xue Liu, Ze-ke Wang, Qing-xu Deng. Design and FPGA Implementation of a Reconfigurable 1024-Channel Channelization Architecture for SDR Application
2462 -- 2474Zhehui Wang, Jiang Xu, Peng Yang, Luan Huu Kinh Duong, Zhifei Wang, Xuan Wang, Zhe Wang, Haoran Li, Rafael Kioji Vivas Maeda. A Holistic Modeling and Analysis of Optical-Electrical Interfaces for Inter/Intra-chip Interconnects
2475 -- 2487Luan H. K. Duong, Zhehui Wang, Mahdi Nikdast, Jiang Xu, Peng Yang, Zhifei Wang, Zhe Wang, Rafael K. V. Maeda, Haoran Li, Xuan Wang, Sébastien Le Beux, Yvain Thonnart. Coherent and Incoherent Crosstalk Noise Analyses in Interchip/Intrachip Optical Interconnection Networks
2488 -- 2501Ryan Gary Kim, Wonje Choi, Zhuo Chen, Partha Pratim Pande, Diana Marculescu, Radu Marculescu. Wireless NoC and Dynamic VFI Codesign: Energy Efficiency Without Performance Penalty
2502 -- 2510Tao Zhang, Ping Gui, Sudipto Chakraborty, Tianwei Liu, Guoying Wu, Paulo Moreira, Filip Tavernier. 10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS
2511 -- 2520Guoying Wu, Deping Huang, Jingxiao Li, Ping Gui, Tianwei Liu, Shita Guo, Rui Wang, Yanli Fan, Sudipto Chakraborty, Mark Morgan. A 1-16 Gb/s All-Digital Clock and Data Recovery With a Wideband High-Linearity Phase Interpolator
2521 -- 2534Woongrae Kim, Chang-Chih Chen, Dae-Hyun Kim, Linda Milor. Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array
2535 -- 2547Sheng-Wei Cheng, Yuan-Hao Chang, Tseng-Yi Chen, Yu-Fen Chang, Hsin-Wen Wei, Wei Kuan Shih. Efficient Warranty-Aware Wear Leveling for Embedded Systems With PCM Main Memory
2548 -- 2561Shouyi Yin, Weizhi Xu, Jiakun Li, Leibo Liu, Shaojun Wei. CWFP: Novel Collective Writeback and Fill Policy for Last-Level DRAM Cache
2562 -- 2569Yunjae Suh, Seungnam Choi, Jae-Yoon Sim. A Low-Power Class-AB Gm-Based Amplifier With Application to an 11-bit Pipelined ADC
2570 -- 2579Young-Hwa Kim, SeongHwan Cho. A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source
2580 -- 2592Marco Ho, Jianping Guo, Tin Wai Mui, Kai Ho Mak, Wang Ling Goh, Hiu Ching Poon, Shi Bu, Ming Wai Lau, Ka Nang Leung. A Two-Stage Large-Capacitive-Load Amplifier With Multiple Cross-Coupled Small-Gain Stages
2593 -- 2597Zhenqi Wei, Peilin Liu, Rongdi Sun, Jun Dai, Zunquan Zhou, Xiangming Geng, Rendong Ying. HAVA: Heterogeneous Multicore ASIP for Multichannel Low-Bit-Rate Vocoder Applications
2598 -- 2602Sheng-Lyang Jang, Wei-Chung Cheng, Ching-Wen Hsue. Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Using Sixth-Order RLC Resonator
2603 -- 2607Jianwei Liu, Yan Zhu 0001, Chi-Hang Chan, Sai-Weng Sin, Seng-Pan U, Rui Paulo da Silva Martins. Uniform Quantization Theory-Based Linearity Calibration for Split Capacitive DAC in an SAR ADC
2608 -- 2612Sachin Kumar, Chip-Hong Chang. n+1}

Volume 24, Issue 6

2013 -- 2025Hong-Son Vu, Kuan-Hung Chen. A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones
2026 -- 2039Tejinder Singh Sandhu, Kamal El-Sankary. A Mismatch-Insensitive Skew Compensation Architecture for Clock Synchronization in 3-D ICs
2040 -- 2049Mohammad Gholami. Total Jitter of Delay-Locked Loops Due to Four Main Jitter Sources
2050 -- 2061Omar Abdelfattah, George Gal, Gordon W. Roberts, Ishiang Shih, Yi-Chi Shih. A Top-Down Design Methodology Encompassing Components Variations Due to Wide-Range Operation in Frequency Synthesizer PLLs
2062 -- 2074Qiang Liu, Qijun Zhang. Accuracy Improvement of Energy Prediction for Solar-Energy-Powered Embedded Systems
2075 -- 2088Yingnan Cui, Wei Zhang, Vivek Chaturvedi, Bingsheng He. Decentralized Thermal-Aware Task Scheduling for Large-Scale Many-Core Systems
2089 -- 2102Muhammad Usman Karim Khan, Muhammad Shafique, Jörg Henkel. Power-Efficient Workload Balancing for Video Applications
2103 -- 2116Inkwon Hwang, Massoud Pedram. A Comparative Study of the Effectiveness of CPU Consolidation Versus Dynamic Voltage and Frequency Scaling in a Virtualized Multicore Server
2117 -- 2127Ashis Maity, Amit Patra. A Single-Stage Low-Dropout Regulator With a Wide Dynamic Range for Generic Applications
2128 -- 2141Fabio Frustaci, David Blaauw, Dennis Sylvester, Massimo Alioto. Approximate SRAMs With Dynamic Energy-Quality Management
2142 -- 2151Sandeep Mishra, Anup Dandapat. EMDBAM: A Low-Power Dual Bit Associative Memory With Match Error and Mask Control
2152 -- 2164Jeongkyu Hong, Soontae Kim. Flexible ECC Management for Low-Cost Transient Error Protection of Last-Level Caches
2165 -- 2173Bo Wang, Qi Li, Tony Tae-Hyoung Kim. Read Bitline Sensing and Fast Local Write-Back Techniques in Hierarchical Bitline Architecture for Ultralow-Voltage SRAMs
2174 -- 2183Wooheon Kang, Changwook Lee, Hyunyul Lim, Sungho Kang. Optimized Built-In Self-Repair for Multiple Memories
2184 -- 2194Fahad Ahmed, Linda S. Milor. Online Measurement of Degradation Due to Bias Temperature Instability in SRAMs
2195 -- 2207Zhong Guan, Malgorzata Marek-Sadowska. Incorporating Process Variations Into SRAM Electromigration Reliability Assessment Using Atomic Flux Divergence
2208 -- 2219Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi, Hirofumi Takishita, Ken Takeuchi. Understanding the Relation Between the Performance and Reliability of nand Flash/SCM Hybrid Solid-State Drive
2220 -- 2233Yao Chen, Swathi T. Gurumani, Yun Liang, Guofeng Li, Donghui Guo, Kyle Rupnow, Deming Chen. FCUDA-NoC: A Scalable and Efficient Network-on-Chip Implementation for the CUDA-to-FPGA Flow
2234 -- 2243Woo-Rham Bae, Gyu-Seob Jeong, Yoonsoo Kim, Hankyu Chi, Deog Kyoon Jeong. Design of Silicon Photonic Interconnect ICs in 65-nm CMOS Technology
2244 -- 2252Sihwan Kim, Jennifer Hasler, Suma George. Integrated Floating-Gate Programming Environment for System-Level ICs
2253 -- 2261Suma George, Sihwan Kim, Sahil Shah, Jennifer Hasler, Michelle Collins, Farhan Adil, Richard B. Wunderlich, Stephen Nease, Shubha Ramakrishnan. A Programmable and Configurable Mixed-Mode FPAA SoC
2262 -- 2274Peng Wang, John McAllister. Streaming Elements for FPGA Signal and Image Processing Accelerators
2275 -- 2285Marzieh Mollaalipour, Hossein Miar Naimi. Design and Analysis of a Highly Efficient Linearized CMOS Subharmonic Mixer for Zero and Low-IF Applications
2286 -- 2298Jae-woong Jeong, Afsaneh Nassery, Jennifer N. Kitchen, Sule Ozev. Built-In Self-Test and Digital Calibration of Zero-IF RF Transceivers
2299 -- 2309Moon Seok Kim, Xueqing Li, Huichu Liu, John Sampson, Suman Datta, Vijaykrishnan Narayanan. Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs
2310 -- 2320Joon-Yeong Lee, Jaehyeok Yang, Jong-Hyeok Yoon, Soon-Won Kwon, Hyosup Won, Jinho Han, Hyeon-Min Bae. A 4×10-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS
2321 -- 2334Ching-Yi Huang, Yun-Jui Li, Chian-Wei Liu, Chun-Yao Wang, Yung-Chih Chen, Suman Datta, Vijaykrishnan Narayanan. Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays
2335 -- 2344Runjie Zhang, Brett H. Meyer, Ke Wang, Mircea R. Stan, Kevin Skadron. Tolerating the Consequences of Multiple EM-Induced C4 Bump Failures
2345 -- 2358Palkesh Jain, Jordi Cortadella, Sachin S. Sapatnekar. A Fast and Retargetable Framework for Logic-IP-Internal Electromigration Assessment Comprehending Advanced Waveform Effects
2359 -- 2368Ramprasath S., Madiwalar Vijaykumar, Vinita Vasudevan. A Skew-Normal Canonical Model for Statistical Static Timing Analysis
2369 -- 2377Javier Hormigo, Julio Villalba. Measuring Improvement When Using HUB Formats to Implement Floating-Point Systems Under Round-to-Nearest
2378 -- 2391Jun Lin, Chenrong Xiong, Zhiyuan Yan. A High Throughput List Decoder Architecture for Polar Codes
2392 -- 2396Irith Pomeranz. Computing Seeds for LFSR-Based Test Generation From Nontest Cubes
2397 -- 2401Hoyoung Tang, Jongsun Park. Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors
2402 -- 2406Antony Xavier Glittas, Mathini Sellathurai, Gopalakrishnan Lakshminarayanan. A Normal I/O Order Radix-2 FFT Architecture to Process Twin Data Streams for MIMO
2407 -- 2411Fang-Ting Chou, Chung-Chih Hung. Glitch Energy Reduction and SFDR Enhancement Techniques for Low-Power Binary-Weighted Current-Steering DAC
2412 -- 0Hong-Son Vu, Kuan-Hung Chen. Corrections to "A Low-Power Broad-Bandwidth Noise Cancellation VLSI Circuit Design for In-Ear Headphones"

Volume 24, Issue 5

1613 -- 1625Ying Wang, Yinhe Han, Huawei Li, Lei Zhang, Yuanqing Cheng, Xiaowei Li 0001. PSI Conscious Write Scheduling: Architectural Support for Reliable Power Delivery in 3-D Die-Stacked PCM
1626 -- 1635Duckhwan Kim, Saibal Mukhopadhyay. Partitioning Methods for Interface Circuit of Heterogeneous 3-D-ICs Under Process Variation
1636 -- 1648Taigon Song, Chang Liu, Yarui Peng, Sung Kyu Lim. Full-Chip Signal Integrity Analysis and Optimization of 3-D ICs
1649 -- 1662Xianmin Chen, Niraj K. Jha. A 3-D CPU-FPGA-DRAM Hybrid Architecture for Low-Power Computation
1663 -- 1674Viveka Konandur Rajanna, Bharadwaj Amrutur. A Variation-Tolerant Replica-Based Reference-Generation Technique for Single-Ended Sensing in Wide Voltage-Range SRAMs
1675 -- 1687Szu-Pang Mu, Mango C.-T. Chao, Shi-Hao Chen, Yi-Ming Wang. Statistical Framework and Built-In Self-Speed-Binning System for Speed Binning Using On-Chip Ring Oscillators
1688 -- 1701Yang Lin, Mark Zwolinski, Basel Halak. A Low-Cost, Radiation-Hardened Method for Pipeline Protection in Microprocessors
1702 -- 1714Mehdi Sadi, Mark Tehranipoor. Design of a Network of Digital Sensor Macros for Extracting Power Supply Noise Profile in SoCs
1715 -- 1727Xiaoxiao Wang, Dongrong Zhang, Donglin Su, LeRoy Winemberg, Mark Tehranipoor. A Novel Peak Power Supply Noise Measurement and Adaptation System for Integrated Circuits
1728 -- 1738Hsuan-Yu Chang, Ching-Yuan Yang. A Reference Voltage Interpolation-Based Calibration Method for Flash ADCs
1739 -- 1748Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. Test Escapes of Stuck-Open Faults Caused by Parasitic Capacitances and Leakage Currents
1749 -- 1760Debao Wei, Libao Deng, Liyan Qiao, Peng Zhang, Xiyuan Peng. PEVA: A Page Endurance Variance Aware Strategy for the Lifetime Extension of NAND Flash
1761 -- 1769Chua-Chin Wang, Deng-Shian Wang, Chiang-Hsiang Liao, Sih-Yu Chen. A Leakage Compensation Design for Low Supply Voltage SRAM
1770 -- 1782Yebin Lee, Soontae Kim. CLAP: Clustered Look-Ahead Prefetching for Energy-Efficient DRAM System
1783 -- 1793Rajendra Bishnoi, Fabian Oboril, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori. Self-Timed Read and Write Operations in STT-MRAM
1794 -- 1807Sandeep Chandran, Smruti R. Sarangi, Preeti Ranjan Panda. Area-Aware Cache Update Trackers for Postsilicon Validation
1808 -- 1820Ming-Chang Yang, Yuan-Hao Chang, Tei-Wei Kuo, Fu-Hsin Chen. Reducing Data Migration Overheads of Flash Wear Leveling in a Progressive Way
1821 -- 1834Ehsan Nasiri, Javeed Shaikh, André Hahn Pereira, Vaughn Betz. Multiple Dice Working as One: CAD Flows and Routing Architectures for Silicon Interposer FPGAs
1835 -- 1848Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, Soon-Jyh Chang. A Systematic Design Methodology of Asynchronous SAR ADCs
1849 -- 1857Zeinab Torabi, Ghassem Jaberipur. Low-Power/Cost RNS Comparison via Partitioning the Dynamic Range
1858 -- 1870Greg Leung, Shaodi Wang, Andrew Pan, Puneet Gupta, Chi On Chui. An Evaluation Framework for Nanotransfer Printing-Based Feature-Level Heterogeneous Integration in VLSI Circuits
1871 -- 1884Chih-Hung Chou, Ta-Wen Kuan, Shovan Barma, Bo-Wei Chen, Wen Ji, Chih-Hsiang Peng, Jhing-Fa Wang. A New Binary-Halved Clustering Method and ERT Processor for ASSR System
1885 -- 1894Kejie Huang, Rong Zhao, Yong Lian. Racetrack Memory-Based Nonvolatile Storage Elements for Multicontext FPGAs
1895 -- 1908Shouyi Yin, Xianqing Yao, Dajiang Liu, Leibo Liu, Shaojun Wei. Memory-Aware Loop Mapping on Coarse-Grained Reconfigurable Architectures
1909 -- 1916Payam Masoumi Farahabadi, Kambiz K. Moez. A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS
1917 -- 1925Fanyi Meng, Kaixue Ma, Kiat Seng Yeo, Shanshan Xu. 2 5-bit Passive Phase Shifter in 65-nm CMOS
1926 -- 1935Basant K. Mohanty, Pramod Kumar Meher, Sujit Kumar Patel. LUT Optimization for Distributed Arithmetic-Based Block Least Mean Square Adaptive Filter
1936 -- 1949Pascal A. Hager, Andrea Bartolini, Luca Benini. Ekho: A 30.3W, 10k-Channel Fully Digital Integrated 3-D Beamformer for Medical Ultrasound Imaging Achieving 298M Focal Points per Second
1950 -- 1961Jesus Omar Lacruz, Francisco Garcia-Herrero, María José Canet, Javier Valls. High-Performance NB-LDPC Decoder With Reduction of Message Exchange
1962 -- 1974Nourhan Bayasi, Temesghen Tekeste, Hani H. Saleh, Baker Mohammad, Ahsan H. Khandoker, Mohammed Ismail. Low-Power ECG-Based Processor for Predicting Ventricular Arrhythmia
1975 -- 1983Immanuel Raja, Gaurab Banerjee, Mohamad A. Zeidan, Jacob A. Abraham. A 0.1-3.5-GHz Duty-Cycle Measurement and Correction Technique in 130-nm CMOS
1984 -- 1992Yung-Hsiang Ho, Chia-Yu Yao. A Low-Jitter Fast-Locked All-Digital Phase-Locked Loop With Phase-Frequency-Error Compensation
1993 -- 1997Chung-Hsien Chang, Shi-Huang Chen, Bo-Wei Chen, Wen Ji, K. Bharanitharan, Jhing-Fa Wang. Fixed-Point Computing Element Design for Transcendental Functions and Primary Operations in Speech Processing
1998 -- 2002Shouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei. Trigger-Centric Loop Mapping on CGRAs
2003 -- 2007Amit Chhabra, Yagnesh Dineshbhai Vaderiya. Low-Energy Power-ON-Reset Circuit for Dual Supply SRAM
2008 -- 2012Abhishek Ambede, A. Prasad Vinod. Design and Implementation of High-Speed All-Pass Transformation-Based Variable Digital Filters by Breaking the Dependence of Operating Frequency on Filter Order

Volume 24, Issue 4

1213 -- 1222Srivatsan Chellappa, Lawrence T. Clark. SRAM-Based Unique Chip Identifier Techniques
1223 -- 1232Lijuan Li, Shuguo Li. m)
1233 -- 1246Ujjwal Guin, Domenic Forte, Mark Tehranipoor. Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling
1247 -- 1256Lauri Koskinen, Markus Hiienkari, Jani Mäkipää, Matthew J. Turnquist. Implementing Minimum-Energy-Point Systems With Adaptive Logic
1257 -- 1265Pramod Kumar Meher. On Efficient Retiming of Fixed-Point Circuits
1266 -- 1279Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Eby G. Friedman, Engin Ipek. Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS
1280 -- 1292S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson. Hybrid LUT/Multiplexer FPGA Logic Architectures
1293 -- 1304Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang. A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory
1305 -- 1318Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei. A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing
1319 -- 1332Jian Kuang 0001, Wing-Kai Chow, Evangeline F. Y. Young. Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs
1333 -- 1341Yong Ye, Yong Kang, Chao Zhang, Yipeng Chan, HanMing Wu, Shiuhwuu Lee, Zhitang Song, Bomy Chen. A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell
1342 -- 1350Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Ki-Ryong Kim, Seong-Ook Jung. Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation
1351 -- 1360Jaeyoung Park, Tianhao Zheng, Mattan Erez, Michael Orshansky. Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture
1361 -- 1370Taehui Na, Jisu Kim, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung. An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM
1371 -- 1376Shivam Verma, Brajesh Kumar Kaushik. Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform
1377 -- 1390Jean-François Pons, Nicolas Dehaese, Sylvain Bourdel, Jean Gaubert, Bruno Paille. RF Power Gating: A Low-Power Technique for Adaptive Radios
1391 -- 1401Jienan Chen, JianHao Hu, Jiangyun Zhou. Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers
1402 -- 1411Yang Zhao, Yilei Shen, Pan Xue, Zhiwei Ma, Zhenfei Peng, Bao-Xing Chen, Zhiliang Hong. An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS
1412 -- 1420Thinh H. Pham, Suhaib A. Fahmy, Ian Vince McLoughlin. Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization
1421 -- 1429Xiao Liang Tan, Pak Kwong Chan. A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation
1430 -- 1440Dong Wang, Xiao Liang Tan, Pak Kwong Chan. A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS
1441 -- 1449Kuan-Ting Lin, Yu-Wei Cheng, Kea-Tiong Tang. A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme
1450 -- 1459Tae-Ho Lee, Yong Hun Kim, Jaehyeong Sim, Jun-Seok Park, Lee-Sup Kim. A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator
1460 -- 1469Mohammad Hossein Taghavi, Peyman Ahmadi, Leonid Belostotski, James W. Haslett. A Stagger-Tuned Transimpedance Amplifier
1470 -- 1483Liang-Jen Chen, Shen-Iuan Liu. A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS
1484 -- 1492Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin-Hyuk Kim, Seong-Ook Jung. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator
1493 -- 1502Ramachandran Venkatasubramanian, Kent Oertle, Sule Ozev. A Comparator-Based Rail Clamp
1503 -- 1514Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. Prebond Testing of Weak Defects in TSVs
1515 -- 1523Caleb Serafy, Avram Bar-Cohen, Ankur Srivastava, Donald Yeung. Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling
1524 -- 1534Xiaoyu Xu, Zhuoxiang Ren, Hui Qu, Dan Ren. 3-D IC Interconnect Capacitance Extraction Using Dual Discrete Geometric Methods With Prism Elements
1535 -- 1545Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania. Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures
1546 -- 1559Weichen Liu, Wei Zhang, Xuan Wang, Jiang Xu. Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip
1560 -- 1573Qiang Liu, Wenqing Ji, Qi Chen, Terrence S. T. Mak. IP Protection of Mesh NoCs Using Square Spiral Routing
1574 -- 1587Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan Huu Kinh Duong, Zhifei Wang, Rafael Kioji Vivas Maeda, Haoran Li. Improve Chip Pin Performance Using Optical Interconnects
1588 -- 1592Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare. Concept, Design, and Implementation of Reconfigurable CORDIC
1593 -- 1597Hooman Farkhani, Ali Peiravi, Farshad Moradi. Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique
1598 -- 1602Hoi Lee. An Auto-Reconfigurable 2×4× AC-DC Regulator for Wirelessly Powered Biomedical Implants With 28% Link Efficiency Enhancement
1603 -- 1606Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro. An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code
1607 -- 1611Jian Wang, Zhonghai Lu, Yubai Li. A New CDMA Encoding/Decoding Method for on-Chip Communication Network
1612 -- 0Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low. n+1}"

Volume 24, Issue 3

813 -- 826Pranav S. Vaidya, John Jaehwan Lee, Vijay S. Pai, Miyoung Lee, Sung Jin Hur. Symbiote Coprocessor Unit - A Streaming Coprocessor for Data Stream Acceleration
827 -- 836Moein Kianpour, Reza Sabbaghi-Nadooshan. A Novel Quantum-Dot Cellular Automata X-bit × 32-bit SRAM
837 -- 845Osama Ullah Khan, David D. Wentzloff. Hardware Accelerator for Probabilistic Inference in 65-nm CMOS
846 -- 857Arnab Raha, Hrishikesh Jayakumar, Vijay Raghunathan. Input-Based Dynamic Reconfiguration of Approximate Arithmetic Units for Video Encoding
858 -- 870Ying Wang, Yinhe Han, Huawei Li, Xiaowei Li. VANUCA: Enabling Near-Threshold Voltage Operation in Large-Capacity Cache
871 -- 883Jongmin Lee 0002, Soontae Kim. Write Buffer-Oriented Energy Reduction in the L1 Data Cache for Embedded Systems
884 -- 896Mahmoud Zangeneh, Ajay Joshi. Designing Tunable Subthreshold Logic Circuits Using Adaptive Feedback Equalization
897 -- 908Eric P. Kim, Jungwook Choi, Naresh R. Shanbhag, Rob A. Rutenbar. Error Resilient and Energy Efficient MRF Message-Passing-Based Stereo Matching
909 -- 919Rabab Ezz-Eldin, Magdy A. El-Moursy, Hesham F. A. Hamed. Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design
920 -- 931Jintao Zheng, Ning Wu, Lei Zhou, Yunfei Ye, Ke Sun. DFSB-Based Thermal Management Scheme for 3-D NoC-Bus Architectures
932 -- 943Mojtaba Ebrahimi, Parthasarathy Murali B. Rao, Razi Seyyedi, Mehdi Baradaran Tahoori. Low-Cost Multiple Bit Upset Correction in SRAM-Based FPGA Configuration Frames
944 -- 953Seyedhamidreza Motaman, Swaroop Ghosh. Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches
954 -- 967Mohammad Reza Jokar, Mohammad Arjomand, Hamid Sarbazi-Azad. Sequoia: A High-Endurance NVM-Based Cache Architecture
968 -- 978Rajiv V. Joshi, Sudesh Saroop, Rouwaida Kanj, Yang Liu, Weike Wang, Carl Radens, Yue Tan, Karthik Yogendra. A Universal Hardware-Driven PVT and Layout-Aware Predictive Failure Analytics for SRAM
979 -- 991Jianxiao Yang, Benoit Geller, Meng Li, Tong Zhang. An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel
992 -- 1002Xuanyao Fong, Rangharajan Venkatesan, Dongsoo Lee, Anand Raghunathan, Kaushik Roy. Embedding Read-Only Memory in Spin-Transfer Torque MRAM-Based On-Chip Caches
1003 -- 1014Yasmin Halawani, Baker Mohammad, Dirar Homouz, Mahmoud Al-Qutayri, Hani H. Saleh. Modeling and Optimization of Memristor and STT-RAM-Based Memory for Low-Power Applications
1015 -- 1024Dong-Hoon Jung, Kyungho Ryu, Jung-Hyun Park, Seong-Ook Jung. All-Digital 90° Phase-Shift DLL With Dithering Jitter Suppression Scheme
1025 -- 1035Won Namgoong. An All-Digital Approach to Supply Noise Cancellation in Digital Phase-Locked Loop
1036 -- 1049Henda Aridhi, Mohamed H. Zaki, Sofiène Tahar. Enhancing Model Order Reduction for Nonlinear Analog Circuit Simulation
1050 -- 1058Ishita Mukhopadhyay, Mustansir Yunus Mukadam, Rajendran Narayanan, Frank O'Mahony, Alyssa B. Apsel. Dual-Calibration Technique for Improving Static Linearity of Thermometer DACs for I/O
1059 -- 1070Yu Zheng, Fengchao Zhang, Swarup Bhunia. DScanPUF: A Delay-Based Physical Unclonable Function Built Into Scan Chain
1071 -- 1082Seyed Amir Reza Ahmadi Mehr, Massoud Tohidian, Robert Bogdan Staszewski. Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division
1083 -- 1091Supeng Liu, Yuanjin Zheng. A Low-Power and Highly Linear 14-bit Parallel Sampling TDC With Power Gating and DEM in 65-nm CMOS
1092 -- 1103Sewook Hwang, Junyoung Song, Sang-Geun Bae, Yeonho Lee, Chulwoo Kim. An Add-On Type Real-Time Jitter Tolerance Enhancer for Digital Communication Receivers
1104 -- 1117Yu Xia, Kaiming Nie, Jiangtao Xu, SuYing Yao. A Two-Step Analog Accumulator for CMOS TDI Image Sensor With Temporal Undersampling Exposure Method
1118 -- 1125Jebreel M. Salem, Dong Sam Ha. Dual Use of Power Lines for Design-for-Testability - A CMOS Receiver Design
1126 -- 1139Aoxiang Tang, Niraj K. Jha. GenFin: Genetic Algorithm-Based Multiobjective Statistical Logic Circuit Optimization Using Incremental Statistical Analysis
1140 -- 1150Kai He, Sheldon X.-D. Tan, Hai Wang, Guoyong Shi. GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis
1151 -- 1164Eric J. Wyers, Matthew A. Morton, T. C. L. Gerhard Sollner, C. T. Kelley, Paul D. Franzon. A Generally Applicable Calibration Algorithm for Digitally Reconfigurable Self-Healing RFICs
1165 -- 1168Hamed Dorosti, Ali Teymouri, Sied Mehdi Fakhraie, Mostafa E. Salehi. Ultralow-Energy Variation-Aware Design: Adder Architecture Study
1169 -- 1173Hsuan-Ming Chou, Yi-Chiao Chen, Keng-Hao Yang, Jean Tsao, Shih-Chieh Chang, Wen-Ben Jone, Tien-Fu Chen. High-Performance Deadlock-Free ID Assignment for Advanced Interconnect Protocols
1174 -- 1178Xiaoyong Xue, Jianguo Yang, Yinyin Lin, Ryan Huang, Qingtian Zou, Jingang Wu. Low-Power Variation-Tolerant Nonvolatile Lookup Table Design
1179 -- 1183Doohwang Chang, Jennifer N. Kitchen, Bertan Bakkaloglu, Sayfe Kiaei, Sule Ozev. Design-Time Reliability Enhancement Using Hotspot Identification for RF Circuits
1184 -- 1188Chan-Keun Kwon, Hoon Ki Kim, Jongsun Park, Soo-Won Kim. A 0.4-mW, 4.7-ps Resolution Single-Loop ΔΣ TDC Using a Half-Delay Time Integrator
1189 -- 1192Chung-Han Chou, Hua-Hsin Yeh, Shih-Hsu Huang, Yow-Tyng Nieh, Shih-Chieh Chang, Yung-Tai Chang. Skew Minimization With Low Power for Wide-Voltage-Range Multipower-Mode Designs
1193 -- 1197Jiliang Zhang. A Practical Logic Obfuscation Technique for Hardware Security
1198 -- 1202Shraddha Bodhe, Enamul Amyeen, Irith Pomeranz, Srikanth Venkataraman. Diagnostic Fail Data Minimization Using an N-Cover Algorithm
1203 -- 1207Yan Zhu 0001, Chi-Hang Chan, Si-Seng Wong, Seng-Pan U, Rui Paulo Martins. Histogram-Based Ratio Mismatch Calibration for Bridge-DAC in 12-bit 120 MS/s SAR ADC
1208 -- 1211Amir Kaivani, Seok-Bum Ko. Floating-Point Butterfly Architecture Based on Binary Signed-Digit Representation
1212 -- 0Kai He, Sheldon X.-D. Tan. Corrections to "GPU-Accelerated Parallel Sparse LU Factorization Method for Fast Circuit Analysis"

Volume 24, Issue 2

413 -- 420Sumedh Dhabu, Vinod Achutavarrier Prasad. Design of Modified Second-Order Frequency Transformations Based Variable Digital Filters With Large Cutoff Frequency Range and Improved Transition Band Characteristics
421 -- 433Milad Bahadori, Mehdi Kamal, Ali Afzali-Kusha, Massoud Pedram. High-Speed and Energy-Efficient Carry Skip Adder Operating Under a Wide Range of Supply Voltage Levels
434 -- 443Shiann-Rong Kuang, Kun-Yi Wu, Ren-Yao Lu. Low-Cost High-Performance VLSI Architecture for Montgomery Modular Multiplication
444 -- 452Basant Kumar Mohanty, Pramod Kumar Meher. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications
453 -- 464Junwhan Ahn, Sungjoo Yoo, Kiyoung Choi. Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching
465 -- 478Masoud Oveis Gharan, Gul N. Khan. Efficient Dynamic Virtual Channel Organization and Architecture for NoC Systems
479 -- 492Evangelia Kasapaki, Martin Schoeberl, Rasmus Bo Sorensen, Christoph Thomas Muller, Kees Goossens, Jens Sparsø. Argo: A Real-Time Network-on-Chip Architecture With an Efficient GALS Implementation
493 -- 506Takahiro Kagami, Hiroki Matsutani, Michihiro Koibuchi, Yasuhiro Take, Tadahiro Kuroda, Hideharu Amano. Efficient 3-D Bus Architectures for Inductive-Coupling ThruChip Interfaces
507 -- 520Shouyi Yin, Dajiang Liu, Yu Peng, Leibo Liu, Shaojun Wei. Improving Nested Loop Pipelining on Coarse-Grained Reconfigurable Architectures
521 -- 529Pilin Junsangsri, Jie Han, Fabrizio Lombardi. Logic-in-Memory With a Nonvolatile Programmable Metallization Cell
530 -- 543Juan Antonio Clemente, Ruben Gran, Abel Chocano, Carlos del Prado, Javier Resano. Hardware Architectural Support for Caching Partitioned Reconfigurations in Reconfigurable Systems
544 -- 554Tao Feng, Nizar Lajnef, Shantanu Chakrabartty. Design of a CMOS System-on-Chip for Passive, Near-Field Ultrasonic Energy Harvesting and Back-Telemetry
555 -- 566Wei Wang, James F. Buckwalter. Source Coding and Preemphasis for Double-Edged Pulsewidth Modulation Serial Communication
567 -- 577Daniel Günther, Rainer Leupers, Gerd Ascheid. Efficiency Enablers of Lightweight SDR for MIMO Baseband Processing
578 -- 586Shuai Chen, Hao Li, Patrick Yin Chiang. A Robust Energy/Area-Efficient Forwarded-Clock Receiver With All-Digital Clock and Data Recovery in 28-nm CMOS for High-Density Interconnects
587 -- 599Chung-An Shen, Chia-Po Yu, Chien-Hao Huang. Algorithm and Architecture of Configurable Joint Detection and Decoding for MIMO Wireless Communications With Convolutional Codes
600 -- 612Insup Shin, Jae-Joon Kim, Yu-Shiang Lin, Youngsoo Shin. One-Cycle Correction of Timing Errors in Pipelines With Standard Clocked Elements
613 -- 624Jinhui Wang, Na Gong, Eby G. Friedman. PNS-FCR: Flexible Charge Recycling Dynamic Circuit Technique for Low-Power Microprocessors
625 -- 637Shu-Yung Bin, Shih-Feng Lin, Ya Ching Cheng, Wen-Rong Liau, Alex Hou, Mango C.-T. Chao. Predicting Shot-Level SRAM Read/Write Margin Based on Measured Transistor Characteristics
638 -- 649Mousumi Bhanja, Baidya Nath Ray. OTA-Based Logarithmic Circuit for Arbitrary Input Signal and Its Application
650 -- 663Morteza Gholipour, Ying-Yu Chen, Amit Sangai, Nasser Masoumi, Deming Chen. Analytical SPICE-Compatible Model of Schottky-Barrier-Type GNRFETs With Performance Analysis
664 -- 677Qiang Liu, Ming Gao, Qijun Zhang. Knowledge-Based Neural Network Model for FPGA Logical Architecture Development
678 -- 691Sadia Alam, S. M. Rezaul Hasan. A VLSI Circuit Emulation of Chemical Synaptic Transmission Dynamics and Postsynaptic DNA Transcription
692 -- 705Vinicius Neves Possani, Vinicius Callegaro, André Inácio Reis, Renato P. Ribas, Felipe de Souza Marques, Leomar Soares da Rosa. Graph-Based Transistor Network Generation Method for Supergate Design
706 -- 719Chen Hou, Qianchuan Zhao. A New Optimal Algorithm for Energy Saving in Embedded System With Multiple Sleep Modes
720 -- 728Jun-Ping Wang, Run-Sen Xing, Dan Xu, Yong-Bang Su, Rui-Ping Feng, Rong Wei, Ya-Ning Li, Teng-Wei Zhao. Redundant Via Insertion Based on SCA
729 -- 742Mehmet Avci, Farid N. Najm. Verification of the Power and Ground Grids Under General and Hierarchical Constraints
743 -- 753Farhad Alibeygi Parsan, Scott C. Smith, Waleed K. Al-Assadi. Design for Testability of Sleep Convention Logic
754 -- 758Jihyuck Jo, Hoyoung Yoo, In-Cheol Park. Energy-Efficient Floating-Point MFCC Extraction Architecture for Speech Recognition Systems
759 -- 763Yung-Hsiang Ho, Chia-Yu Yao. A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation Register
764 -- 768Jinyoung Kim, Sang-Hoon Park, Hyeokjun Seo, Ki-Whan Song, Sungroh Yoon, Eui-Young Chung. NAND Flash Memory With Multiple Page Sizes for High-Performance Storage Devices
769 -- 773Zhen Gao, Pedro Reviriego, Zhan Xu, Xin Su, Ming Zhao, Jing Wang, Juan Antonio Maestro. Fault Tolerant Parallel FFTs Using Error Correction Codes and Parseval Checks
774 -- 778Alexander Shapiro, Eby G. Friedman. Power Efficient Level Shifter for 16 nm FinFET Near Threshold Circuits
779 -- 783Hao Xiao, Ning Wu, Fen Ge, Tsuyoshi Isshiki, Hiroaki Kunieda, Jun Xu, Yuangang Wang. Efficient Synchronization for Distributed Embedded Multiprocessors
784 -- 788Tong-Yu Hsieh, Chih-Hao Wang, Tsung-Liang Chih, Ya-Hsiu Chi. A Performance Degradation Tolerable Cache Design by Exploiting Memory Hierarchies
789 -- 793Yong Hun Kim, Young-Ju Kim 0001, Tae-Ho Lee, Lee-Sup Kim. A 21-Gbit/s 1.63-pJ/bit Adaptive CTLE and One-Tap DFE With Single Loop Spectrum Balancing Method
794 -- 798Si-Nai Kim, Mee-Ran Kim, Ba-Ro-Saim Sung, Hyun-Wook Kang, Min Hyung Cho, Seung-Tak Ryu. 2
799 -- 802Victor Dumitriu, Lev Kirischian. SoPC Self-Integration Mechanism for Seamless Architecture Adaptation to Stream Workload Variations
803 -- 807Amirreza Alizadeh, Reza Sarvari. Temperature-Dependent Comparison Between Delay of CNT and Copper Interconnects
808 -- 812M. Hassan Najafi, Mostafa E. Salehi. A Fast Fault-Tolerant Architecture for Sauvola Local Image Thresholding Algorithm Using Stochastic Computing

Volume 24, Issue 12

3373 -- 3386Zhe Wang, Xuan Wang, Jiang Xu, Haoran Li, Rafael K. V. Maeda, Zhehui Wang, Peng Yang, Luan H. K. Duong, Zhifei Wang. An Adaptive Process-Variation-Aware Technique for Power-Gating-Induced Power/Ground Noise Mitigation in MPSoC
3387 -- 3400Fahimeh Jafari, Axel Jantsch, Zhonghai Lu. Weighted Round Robin Configuration for Worst-Case Delay Optimization in Network-on-Chip
3401 -- 3414Vivek Joy Kozhikkottu, Rangharajan Venkatesan, Anand Raghunathan, Sujit Dey. Emulation-Based Analysis of System-on-Chip Performance Under Variations
3415 -- 3423Jun Wang, Jianmin Lu, Yang Liu, Xiuqin Chu, YuShan Li. Effective Radii of On-Chip Decoupling Capacitors Under Noise Constraint
3424 -- 3436Xiaolu Wang, Huaxi Gu, Yintang Yang, Kun Wang, Qinfen Hao. A Highly Scalable Optical Network-on-Chip With Small Network Diameter and Deadlock Freedom
3437 -- 3449Wei-Hen Lo, Kang Chi, TingTing Hwang. Architecture of Ring-Based Redundant TSV for Clustered Faults
3450 -- 3459Robert Polster, Yvain Thonnart, Guillaume Waltener, Jose-Luis Gonzalez Jimenez, Eric Cassan. Efficiency Optimization of Silicon Photonic Links in 65-nm CMOS and 28-nm FDSOI Technology Nodes
3460 -- 3467Pai-Yu Chen, Zhiwei Li, Shimeng Yu. Design Tradeoffs of Vertical RRAM-Based 3-D Cross-Point Array
3468 -- 3476Ayan Paul, Sang Phill Park, Dinesh Somasekhar, Young Moon Kim, Nitin Borkar, Ulya R. Karpuzcu, Chris H. Kim. System-Level Power Analysis of a Multicore Multipower Domain Processor With ON-Chip Voltage Regulators
3477 -- 3488Jin-Wei Jhang, Yuan-Hao Huang. A High-SNR Projection-Based Atom Selection OMP Processor for Compressive Sensing
3489 -- 3498Sadegh Yazdanshenas, Behnam Khaleghi, Paolo Ienne, Hossein Asadi. Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays
3499 -- 3512Chenrong Xiong, Jun Lin, Zhiyuan Yan. A Multimode Area-Efficient SCL Polar Decoder
3513 -- 3525Yongsheng Xu, Ge Wu, Leonid Belostotski, James W. Haslett. 5-bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications
3526 -- 3537Robert Karam, Ruchir Puri, Swarup Bhunia. Energy-Efficient Adaptive Hardware Accelerator for Text Mining Application Kernels
3538 -- 3542Alfonso Sánchez-Macián, Pedro Reviriego, Juan Antonio Maestro. Optimizing the Implementation of SEC-DAEC Codes in FPGAs
3543 -- 3547Chundong Wu, Wang Ling Goh, Chiang Liang Kok, Liter Siek, Yat-Hei Lam, Xi Zhu, Ravinder Pal Singh. Asymmetrical Dead-Time Control Driver for Buck Regulator
3548 -- 3552Sebastian Höppner, Johannes Partzsch, Johannes Neumann, René Schüffny, Christian Mayr. A Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution Monitoring

Volume 24, Issue 11

3193 -- 3207Sanjeev Das, Wei Zhang, Yang Liu. A Fine-Grained Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded Systems
3208 -- 3217Giovanni Causapruno, Fabrizio Riente, Giovanna Turvani, Marco Vacca, Massino Ruo Roch, Maurizio Zamboni, Mariagrazia Graziano. Reconfigurable Systolic Array: From Architecture to Physical Design for NML
3218 -- 3231Aida Todri-Sanial, Yuanqing Cheng. A Study of 3-D Power Delivery Networks With Multiple Clock Domains
3232 -- 3242Young-Jae An, Dong-Hoon Jung, Kyungho Ryu, Hyuck-Sang Yim, Seong-Ook Jung. All-Digital ON-Chip Process Sensor Using Ratioed Inverter-Based Ring Oscillator
3243 -- 3256Junshi Liu, Swagath Venkataramani, Singanallur V. Venkatakrishnan, Yun Pan, Charles A. Bouman, Anand Raghunathan. EMBIRA: An Accelerator for Model-Based Iterative Reconstruction
3257 -- 3267Miroslav Knezevic, Ventzislav Nikov, Peter Rombouts. Low-Latency ECDSA Signature Verification - A Road Toward Safer Traffic
3268 -- 3281Yavar Safaei Mehrabani, Mohammad Eshghi. Noise and Process Variation Tolerant, Low-Power, High-Speed, and Low-Energy Full Adders in CNFET Technology
3282 -- 3295Yousuke Miyake, Yasuo Sato, Seiji Kajihara, Yukiya Miura. Temperature and Voltage Measurement for Field Test Using an Aging-Tolerant Monitor
3296 -- 3309Hamed Farbeh, Nooshin Sadat Mirzadeh, Nahid Farhady Ghalaty, Seyed Ghassem Miremadi, Mahdi Fazeli, Hossein Asadi. A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction
3310 -- 3322Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao. Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect
3323 -- 3333Chih-Feng Wu, Wei-Chang Liu, Chia-Chun Tsui, Chun-Yi Liu, Meng-Siou Sie, Shyh-Jye Jou. Golay-Correlator Window-Based Noise Cancellation Equalization Technique for 60-GHz Wireless OFDM/SC Receiver
3334 -- 3344Yung-Hui Chung, Chia-Wei Yen, Meng-Hsuan Wu. A 24- μW 12-bit 1-MS/s SAR ADC With Two-Step Decision DAC Switching in 110-nm CMOS
3345 -- 3358Pranab Roy, Swati Saha, Hafizur Rahaman, Parthasarathi Dasgupta. Novel Wire Planning Schemes for Pin Minimization in Digital Microfluidic Biochips
3359 -- 3372Jim Ng, Xiaohang Wang, Amit Kumar Singh, Terrence S. T. Mak. Defragmentation for Efficient Runtime Resource Management in NoC-Based Many-Core Systems

Volume 24, Issue 10

3013 -- 3026Xianmin Chen, Niraj K. Jha. Reducing Wire and Energy Overheads of the SMART NoC Using a Setup Request Network
3027 -- 3040Lei Yang 0018, Weichen Liu, Weiwen Jiang, Mengquan Li, Juan Yi, Edwin Hsing-Mean Sha. Application Mapping and Scheduling for Network-on-Chip-Based Multiprocessor System-on-Chip With Fine-Grain Communication Optimization
3041 -- 3054Jia Zhan, Jin Ouyang, Fen Ge, Jishen Zhao, Yuan Xie 0001. Hybrid Drowsy SRAM and STT-RAM Buffer Designs for Dark-Silicon-Aware NoC
3055 -- 3066Andreas Riefert, Riccardo Cantoro, Matthias Sauer, Matteo Sonza Reorda, Bernd Becker. A Flexible Framework for the Automatic Generation of SBST Programs
3067 -- 3079Nan Wang, Wei Zhong, Cong Hao, Song Chen, Takeshi Yoshimura, Yu Zhu. Leakage-Power-Aware Scheduling With Dual-Threshold Voltage Design
3080 -- 3093Can Sitik, Weicheng Liu, Baris Taskin, Emre Salman. Design Methodology for Voltage-Scaled Clock Distribution Networks
3094 -- 3104Xianzhang Chen, Edwin Hsing-Mean Sha, Qingfeng Zhuge, Chun Jason Xue, Weiwen Jiang, Yuangang Wang. Efficient Data Placement for Improving Data Access Performance on Domain-Wall Memory
3105 -- 3117Georgios Zervakis, Kostas Tsoumanis, Sotirios Xydis, Dimitrios Soudris, Kiamal Z. Pekmestzi. Design-Efficient Approximate Multiplication Circuits Through Partial Product Perforation
3118 -- 3131Seunghan Lee, Kyungsu Kang, Jongpil Jung, Chong-Min Kyung. Hybrid L2 NUCA Design and Management Considering Data Access Latency, Energy Efficiency, and Storage Lifetime
3132 -- 3144Ming-Chang Yang, Yuan-Hao Chang, Chei-Wei Tsao, Chung-Yu Liu. Utilization-Aware Self-Tuning Design for TLC Flash Storage Devices
3145 -- 3155Debao Wei, Liyan Qiao, Shiyuan Wang, Xiyuan Peng. Fixation Ratio of Error Location-Aware Strategy for Increased Reliable Retention Time of Flash Memory
3156 -- 3168Tsung-Hsueh Lee, Pamela Abshire. Frequency-Boost Jitter Reduction for Voltage-Controlled Ring Oscillators
3169 -- 3183Ran Wang, Jie Han, Bruce F. Cockburn, Duncan G. Elliott. Stochastic Circuit Design and Performance Evaluation of Vector Quantization for Different Error Measures
3184 -- 3192Sen Wang, Chih-Hsuan Lee, Yan-bin Wu. Fully Integrated 10-GHz Active Circulator and Quasi-Circulator Using Bridged-T Networks in Standard CMOS

Volume 24, Issue 1

3 -- 16Nishit Ashok Kapadia, Sudeep Pasricha. A System-Level Cosynthesis Framework for Power Delivery and On-Chip Data Networks in Application-Specific 3-D ICs
17 -- 25Wei-Cheng Chen, Chao-Chyun Chen, Chia-Yu Yao, Rong-Jyi Yang. A Fast-Transient Wide-Voltage-Range Digital-Controlled Buck Converter With Cycle-Controlled DPWM
26 -- 37Mohammadreza Ashraf, Nasser Masoumi. A Thermal Energy Harvesting Power Supply With an Internal Startup Circuit for Pacemakers
38 -- 49Wei-Sheng Ding, Hung-Yi Hsieh, Cheng-Yu Han, James Chien-Mo Li, Xiaoqing Wen. Test Pattern Modification for Average IR-Drop Reduction
50 -- 57Tay-Jyi Lin, Ting-Yu Shyu. Speculative Lookahead for Energy-Efficient Microprocessors
58 -- 66Brian P. Degnan, Bo Marr, Jennifer Hasler. Assessing Trends in Performance per Watt for Signal Processing Applications
67 -- 78Jian Wang, Chunlin Xiong, Kangli Zhang, Jibo Wei. k Parallel FFT
79 -- 91Qi Guo, Xi Li, Chao Wang, Xuehai Zhou. Evaluation and Tradeoffs for Out-of-Order Execution on Reconfigurable Heterogeneous MPSoC
92 -- 102Yinhe Han, Jianbo Dong, Kaiheng Weng, Ying Wang, Xiaowei Li. Enhanced Wear-Rate Leveling for PRAM Lifetime Improvement Considering Process Variation
103 -- 114Sparsh Mittal, Jeffrey S. Vetter. EqualWrites: Reducing Intra-Set Write Variations for Enhancing Lifetime of Non-Volatile Caches
115 -- 128Chao Sun, Ayumi Soga, Chihiro Matsui, Asuka Arakawa, Ken Takeuchi. LBA Scrambler: A NAND Flash Aware Data Management Scheme for High-Performance Solid-State Drives
129 -- 138Ravi Patel, Xiaochen Guo, Qing Guo, Engin Ipek, Eby G. Friedman. Reducing Switching Latency and Energy in STT-MRAM Caches With Field-Assisted Writing
139 -- 150Kejie Huang, Rong Zhao, Wei He, Yong Lian. High-Density and High-Reliability Nonvolatile Field-Programmable Gate Array With Stacked 1D2R RRAM Array
151 -- 164Hamad Marzouqi, Mahmoud Al-Qutayri, Khaled Salah, Dimitrios Schinianakis, Thanos Stouraitis. A High-Speed FPGA Implementation of an RSD-Based ECC Processor
165 -- 177Mohamed S. Abdelfattah, Vaughn Betz. Power Analysis of Embedded NoCs on FPGAs and Comparison With Custom Buses
178 -- 191Assem A. M. Bsoul, Steven J. E. Wilton, Kuen Hung Tsoi, Wayne Luk. An FPGA Architecture and CAD Flow Supporting Dynamically Controlled Power Gating
192 -- 205Shaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta. PROCEED: A Pareto Optimization-Based Circuit-Level Evaluator for Emerging Devices
206 -- 217Ioannis Vourkas, Dimitrios Stathis, Georgios Ch. Sirakoulis, Said Hamdioui. Alternative Architectures Toward Reliable Memristive Crossbar Memories
218 -- 222Mohit Kumar Gupta, Mohd Hasan. A Low-Power Robust Easily Cascaded PentaMTJ-Based Combinational and Sequential Circuits
223 -- 232Meysam Asghari, Mohammad Yavari. Using the Gate-Bulk Interaction and a Fundamental Current Injection to Attenuate IM3 and IM2 Currents in RF Transconductors
233 -- 242Neelanjana Pal, Prajit Nandi, Riju Biswas, Ashvinkumar G. Katakwar. Placement-Based Nonlinearity Reduction Technique for Differential Current-Steering DAC
243 -- 255Yang Xu, Zehong Zhang, Baoyong Chi, Nan Qi, Hualin Cai, Zhihua Wang. A 5-/20-MHz BW Reconfigurable Quadrature Bandpass CT ΔΣ ADC With AntiPole-Splitting Opamp and Digital I/Q Calibration
256 -- 265Maryam Zare, Mohammad Maymandi-Nejad. A Fully Digital Front-End Architecture for ECG Acquisition System With 0.5 V Supply
266 -- 275Wei Jhih Wang, Chang Hong Lin. Code Compression for Embedded Systems Using Separated Dictionaries
276 -- 289Jedrzej Kufel, Peter R. Wilson, Stephen Hill, Bashir M. Al-Hashimi, Paul N. Whatmough. Sequence-Aware Watermark Design for Soft IP Embedded Processors
290 -- 300Chuang Bai, Xuecheng Zou, Kui Dai. A Novel Thyristor-Based Silicon Physical Unclonable Function
301 -- 312Benjamin Carrión Schäfer. Source Code Error Detection in High-Level Synthesis Functional Verification
313 -- 323Kamran Rahmani, Sudhi Proch, Prabhat Mishra. Efficient Selection of Trace and Scan Signals for Post-Silicon Debug
324 -- 328Benjamin Carrión Schäfer. Tunable Multiprocess Mapping on Coarse-Grain Reconfigurable Architectures With Dynamic Frequency Control
329 -- 333Debajit Bhattacharya, Niraj K. Jha. TCAD-Assisted Capacitance Extraction of FinFET SRAM and Logic Arrays
334 -- 337Liang Shi, Yejia Di, Mengying Zhao, Chun Jason Xue, Kaijie Wu, Edwin Hsing-Mean Sha. Exploiting Process Variation for Write Performance Improvement on NAND Flash Memory Storage Systems
338 -- 342Qingqing Yang, Xiaofang Zhou, Gerald E. Sobelman, Xinxin Li. Network-on-Chip for Turbo Decoders
343 -- 347Michael Moeng, Haifeng Xu, Rami G. Melhem, Alex K. Jones. ContextPreRF: Enhancing the Performance and Energy of GPUs With Nonuniform Register Access
348 -- 352Oscal T.-C. Chen, Cheng-Ta Chan, Robin R.-B. Sheen. Transimpedance Limit Exploration and Inductor-Less Bandwidth Extension for Designing Wideband Amplifiers
353 -- 357Jens Muller, Jan Muller, Robert Braunschweig, Ronald Tetzlaff. A Cellular Network Architecture With Polynomial Weight Functions
358 -- 362Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish. Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications
363 -- 367Chan-Hui Jeong, Ammar Abdullah, Young-Jae Min, In-Chul Hwang, Soo-Won Kim. All-Digital Duty-Cycle Corrector With a Wide Duty Correction Range for DRAM Applications
368 -- 372Kostas Tsoumanis, Sotirios Xydis, Georgios Zervakis, Kiamal Z. Pekmestzi. Flexible DSP Accelerator Architecture Exploiting Carry-Save Arithmetic
373 -- 377C. B. Kushwah, Santosh Kumar Vishvakarma. A Single-Ended With Dynamic Feedback Control 8T Subthreshold SRAM Cell
378 -- 382Jesus Moreno, Michel Renovell, Víctor H. Champac. Effectiveness of Low-Voltage Testing to Detect Interconnect Open Defects Under Process Variations
383 -- 387Vianney Lapotre, Purushotham Murugappa, Guy Gogniat, Amer Baghdadi, Michael Hübner, Jean-Philippe Diguet. A Dynamically Reconfigurable Multi-ASIP Architecture for Multistandard and Multimode Turbo Decoding
388 -- 392Jaeyong Chung, Woochul Kang. Defect Diagnosis via Segment Delay Learning
393 -- 397Bibhas Ghoshal, Kanchan Manna, Santanu Chattopadhyay, Indranil Sengupta. In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers
398 -- 402Tooraj Nikoubin, Mahdieh Grailoo, Changzhi Li. Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology
403 -- 407Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen. Polymorphic Configuration Architecture for CGRAs
408 -- 412Ching-Che Chung, Wei-Siang Su, Chi-Kuang Lo. A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling