1213 | -- | 1222 | Srivatsan Chellappa, Lawrence T. Clark. SRAM-Based Unique Chip Identifier Techniques |
1223 | -- | 1232 | Lijuan Li, Shuguo Li. m) |
1233 | -- | 1246 | Ujjwal Guin, Domenic Forte, Mark Tehranipoor. Design of Accurate Low-Cost On-Chip Structures for Protecting Integrated Circuits Against Recycling |
1247 | -- | 1256 | Lauri Koskinen, Markus Hiienkari, Jani Mäkipää, Matthew J. Turnquist. Implementing Minimum-Energy-Point Systems With Adaptive Logic |
1257 | -- | 1265 | Pramod Kumar Meher. On Efficient Retiming of Fixed-Point Circuits |
1266 | -- | 1279 | Yuxin Bai, Yanwei Song, Mahdi Nazm Bojnordi, Alexander E. Shapiro, Eby G. Friedman, Engin Ipek. Back to the Future: Current-Mode Processor in the Era of Deeply Scaled CMOS |
1280 | -- | 1292 | S. Alexander Chin, Jason Luu, Safeen Huda, Jason Helge Anderson. Hybrid LUT/Multiplexer FPGA Logic Architectures |
1293 | -- | 1304 | Kin-Chu Ho, Chih-Lung Chen, Hsie-Chia Chang. A 520k (18900, 17010) Array Dispersion LDPC Decoder Architectures for NAND Flash Memory |
1305 | -- | 1318 | Shouyi Yin, Peng Ouyang, Tianbao Chen, Leibo Liu, Shaojun Wei. A Configurable Parallel Hardware Architecture for Efficient Integral Histogram Image Computing |
1319 | -- | 1332 | Jian Kuang 0001, Wing-Kai Chow, Evangeline F. Y. Young. Triple Patterning Lithography Aware Optimization and Detailed Placement Algorithms for Standard Cell-Based Designs |
1333 | -- | 1341 | Yong Ye, Yong Kang, Chao Zhang, Yipeng Chan, HanMing Wu, Shiuhwuu Lee, Zhitang Song, Bomy Chen. A 40-nm 16-Mb Contact-Programming Mask ROM Using Dual Trench Isolation Diode Bitcell |
1342 | -- | 1350 | Kyoman Kang, Hanwool Jeong, Younghwi Yang, Juhyun Park, Ki-Ryong Kim, Seong-Ook Jung. Full-Swing Local Bitline SRAM Architecture Based on the 22-nm FinFET Technology for Low-Voltage Operation |
1351 | -- | 1360 | Jaeyoung Park, Tianhao Zheng, Mattan Erez, Michael Orshansky. Variation-Tolerant Write Completion Circuit for Variable-Energy Write STT-RAM Architecture |
1361 | -- | 1370 | Taehui Na, Jisu Kim, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung. An Offset-Tolerant Dual-Reference-Voltage Sensing Scheme for Deep Submicrometer STT-RAM |
1371 | -- | 1376 | Shivam Verma, Brajesh Kumar Kaushik. Low-Power High-Density STT MRAMs on a 3-D Vertical Silicon Nanowire Platform |
1377 | -- | 1390 | Jean-François Pons, Nicolas Dehaese, Sylvain Bourdel, Jean Gaubert, Bruno Paille. RF Power Gating: A Low-Power Technique for Adaptive Radios |
1391 | -- | 1401 | Jienan Chen, JianHao Hu, Jiangyun Zhou. Hardware and Energy-Efficient Stochastic LU Decomposition Scheme for MIMO Receivers |
1402 | -- | 1411 | Yang Zhao, Yilei Shen, Pan Xue, Zhiwei Ma, Zhenfei Peng, Bao-Xing Chen, Zhiliang Hong. An All-Digital Gigahertz Class-S Transmitter in a 65-nm CMOS |
1412 | -- | 1420 | Thinh H. Pham, Suhaib A. Fahmy, Ian Vince McLoughlin. Efficient Integer Frequency Offset Estimation Architecture for Enhanced OFDM Synchronization |
1421 | -- | 1429 | Xiao Liang Tan, Pak Kwong Chan. A Fully Integrated Point-of-Load Digital System Supply With PVT Compensation |
1430 | -- | 1440 | Dong Wang, Xiao Liang Tan, Pak Kwong Chan. A Performance-Aware MOSFET Threshold Voltage Measurement Circuit in a 65-nm CMOS |
1441 | -- | 1449 | Kuan-Ting Lin, Yu-Wei Cheng, Kea-Tiong Tang. A 0.5 V 1.28-MS/s 4.68-fJ/Conversion-Step SAR ADC With Energy-Efficient DAC and Trilevel Switching Scheme |
1450 | -- | 1459 | Tae-Ho Lee, Yong Hun Kim, Jaehyeong Sim, Jun-Seok Park, Lee-Sup Kim. A 5-Gb/s 2.67-mW/Gb/s Digital Clock and Data Recovery With Hybrid Dithering Using a Time-Dithered Delta-Sigma Modulator |
1460 | -- | 1469 | Mohammad Hossein Taghavi, Peyman Ahmadi, Leonid Belostotski, James W. Haslett. A Stagger-Tuned Transimpedance Amplifier |
1470 | -- | 1483 | Liang-Jen Chen, Shen-Iuan Liu. A 12-bit 3.4 MS/s Two-Step Cyclic Time-Domain ADC in 0.18-µm CMOS |
1484 | -- | 1492 | Kyungho Ryu, Jiwan Jung, Dong-Hoon Jung, Jin-Hyuk Kim, Seong-Ook Jung. High-Speed, Low-Power, and Highly Reliable Frequency Multiplier for DLL-Based Clock Generator |
1493 | -- | 1502 | Ramachandran Venkatasubramanian, Kent Oertle, Sule Ozev. A Comparator-Based Rail Clamp |
1503 | -- | 1514 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras. Prebond Testing of Weak Defects in TSVs |
1515 | -- | 1523 | Caleb Serafy, Avram Bar-Cohen, Ankur Srivastava, Donald Yeung. Unlocking the True Potential of 3-D CPUs With Microfluidic Cooling |
1524 | -- | 1534 | Xiaoyu Xu, Zhuoxiang Ren, Hui Qu, Dan Ren. 3-D IC Interconnect Capacitance Extraction Using Dual Discrete Geometric Methods With Prism Elements |
1535 | -- | 1545 | Andrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania. Runtime Tunable Transmitting Power Technique in mm-Wave WiNoC Architectures |
1546 | -- | 1559 | Weichen Liu, Wei Zhang, Xuan Wang, Jiang Xu. Distributed Sensor Network-on-Chip for Performance Optimization of Soft-Error-Tolerant Multiprocessor System-on-Chip |
1560 | -- | 1573 | Qiang Liu, Wenqing Ji, Qi Chen, Terrence S. T. Mak. IP Protection of Mesh NoCs Using Square Spiral Routing |
1574 | -- | 1587 | Zhehui Wang, Jiang Xu, Peng Yang, Xuan Wang, Zhe Wang, Luan Huu Kinh Duong, Zhifei Wang, Rafael Kioji Vivas Maeda, Haoran Li. Improve Chip Pin Performance Using Optical Interconnects |
1588 | -- | 1592 | Supriya Aggarwal, Pramod Kumar Meher, Kavita Khare. Concept, Design, and Implementation of Reconfigurable CORDIC |
1593 | -- | 1597 | Hooman Farkhani, Ali Peiravi, Farshad Moradi. Low-Energy Write Operation for 1T-1MTJ STT-RAM Bitcells With Negative Bitline Technique |
1598 | -- | 1602 | Hoi Lee. An Auto-Reconfigurable 2×4× AC-DC Regulator for Wirelessly Powered Biomedical Implants With 28% Link Efficiency Enhancement |
1603 | -- | 1606 | Pedro Reviriego, Shanshan Liu, Liyi Xiao, Juan Antonio Maestro. An Efficient Single and Double-Adjacent Error Correcting Parallel Decoder for the (24, 12) Extended Golay Code |
1607 | -- | 1611 | Jian Wang, Zhonghai Lu, Yubai Li. A New CDMA Encoding/Decoding Method for on-Chip Communication Network |
1612 | -- | 0 | Thian Fatt Tay, Chip-Hong Chang, Jeremy Yung Shern Low. n+1}" |