| 815 | -- | 842 | Massimo Alioto. Second Quarter of the 2021 Editorial Year - A Year in Crescendo |
| 843 | -- | 856 | Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal 0001, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim. Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities |
| 857 | -- | 870 | Rui Zhang 0048, Kexin Yang, Zhaocheng Liu, Taizhi Liu, Wenshan Cai, Linda Milor. A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory |
| 871 | -- | 882 | Azad Mahmoudi, Pooya Torkzadeh, Massoud Dousti. A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications |
| 883 | -- | 894 | Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang. A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links |
| 895 | -- | 903 | Jian Liu, Shubin Liu, Ruixue Ding, Zhangming Zhu. A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems |
| 904 | -- | 915 | Hsun-Wei Chan, Wei-Che Lee, Kang-Lun Chiu, Chih-Wei Jen, Shyh-Jye Jou. A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems |
| 916 | -- | 924 | Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri. High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register |
| 925 | -- | 935 | Nima Taherinejad. SIXOR: Single-Cycle In-Memristor XOR |
| 936 | -- | 949 | Di Wu, Xitian Fan, Wei Cao 0002, Lingli Wang. SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator |
| 950 | -- | 961 | Fatima Hameed Khan, Wala Saadeh. An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia |
| 962 | -- | 972 | Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis. Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance |
| 973 | -- | 984 | Jai-Ming Lin, You-Lun Deng, Ya Chu Yang, Jia-Jian Chen, Po-Chen Lu. Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs |
| 985 | -- | 997 | Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu. Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation |
| 998 | -- | 1008 | Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo. A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops |
| 1009 | -- | 1021 | Biswajit Bhowmik. Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks |
| 1022 | -- | 1032 | Heng You, Jia Yuan, Zenghui Yu, Shushan Qiao. Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation |
| 1033 | -- | 1037 | Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh. m) |