External Links

    Journal: IEEE Trans. VLSI Syst.

    Volume 29, Issue 9

    1601 -- 1611Meysam Akbari, Safwan Mawlood Hussein, Yasir Hashim, Kea-Tiong Tang. An Enhanced Input Differential Pair for Low-Voltage Bulk-Driven Amplifiers
    1612 -- 1623Nikos Temenos, Paul P. Sotiriadis. Nonscaling Adders and Subtracters for Stochastic Computing Using Markov Chains
    1624 -- 1637Gianna Paulin, Renzo Andri, Francesco Conti 0001, Luca Benini. RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures
    1638 -- 1651Qingkun Chen, Wenjin Huang, Yuze Peng, Yihua Huang. A Reinforcement Learning-Based Framework for Solving the IP Mapping Problem
    1652 -- 1664Jai-Ming Lin, Wei-Yi Chang, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu. Thermal-Aware Floorplanning and TSV-Planning for Mixed-Type Modules in a Fixed-Outline 3-D IC
    1665 -- 1669Jiangchao Wu, Hou-Man Leong, Yang Jiang 0002, Man Kay Law, Pui-In Mak, Rui Paulo Martins. A Fully Integrated 10-V Pulse Driver Using Multiband Pulse-Frequency Modulation in 65-nm CMOS
    1670 -- 1674Jiajing Gao, Wei Zhang 0055, Yanyan Liu, Hao Wang 0072, Jianhan Zhao. High-Performance Concatenation Decoding of Reed-Solomon Codes With SPC Codes
    1675 -- 1679Abhijit Das 0002, John Jose, Prabhat Mishra 0001. Data Criticality in Multithreaded Applications: An Insight for Many-Core Systems
    1680 -- 1684Gwangho Lee, SunWoo Lee, Dongsuk Jeon. Dynamic Block-Wise Local Learning Algorithm for Efficient Neural Network Training

    Volume 29, Issue 8

    1505 -- 1517Ahmet Turan Erozan, Simon Bosse, Mehdi B. Tahoori. Defect Detection in Transparent Printed Electronics Using Learning-Based Optical Inspection
    1518 -- 1528Karthikeyan Nagarajan, Farid Uddin Ahmed, Mohammad Nasim Imtiaz Khan, Asmit De, Masud H. Chowdhury, Swaroop Ghosh. SecNVM: Power Side-Channel Elimination Using On-Chip Capacitors for Highly Secure Emerging NVM
    1529 -- 1542Abdulrahman Alaql, Md Moshiur Rahman 0001, Swarup Bhunia. SCOPE: Synthesis-Based Constant Propagation Attack on Logic Locking
    1543 -- 1552Prashansa Mukim, Forrest Brewer. Multiwire Phase Encoding: A Signaling Strategy for High-Bandwidth, Low-Power Data Movement
    1553 -- 1566Yingdi Liu, Sylwester Milewski, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Janusz Rajski, Jerzy Tyszer, Bartosz Wlodarczak. X-Tolerant Compactor maXpress for In-System Test Applications With Observation Scan
    1567 -- 1574Junyoung Song, Sewook Hwang, Chulwoo Kim. A 32-Gb/s Dual-Mode Transceiver With One-Tap FIR and Two-Tap IIR RX Only Equalization in 65-nm CMOS Technology
    1575 -- 1585Chuanshi Yang, Erik Olieman, Alphons Litjes, Lei Qiu 0002, Kai Tang, Yuanjin Zheng, Robert H. M. van Veldhoven. An Area-Efficient SAR ADC With Mismatch Error Shaping Technique Achieving 102-dB SFDR 90.2-dB SNDR Over 20-kHz Bandwidth
    1586 -- 1590Chi-Ray Huang, Lih-Yih Chiou. An Energy-Efficient Conditional Biasing Write Assist With Built-In Time-Based Write-Margin-Tracking for Low-Voltage SRAM
    1591 -- 1595Zhifei Lu, He Tang, Zhaofeng Ren, Ruogu Hua, Haoyu Zhuang, Xizhu Peng. A Timing Mismatch Background Calibration Algorithm With Improved Accuracy
    1596 -- 1600Sarah Azimi, Corrado De Sio, Luca Sterpone. A Radiation-Hardened CMOS Full-Adder Based on Layout Selective Transistor Duplication

    Volume 29, Issue 7

    1285 -- 1296Ivan Miketic, Emre Salman. PhaseCamouflage: Leveraging Adiabatic Operation to Thwart Reverse Engineering
    1297 -- 1305Mojtaba Bisheh Niasar, Reza Azarderakhsh, Mehran Mozaffari Kermani. Cryptographic Accelerators for Digital Signature Based on Ed25519
    1306 -- 1318Christian Pilato, Animesh Basak Chowdhury, Donatella Sciuto, Siddharth Garg, Ramesh Karri. ASSURE: RTL Locking Against an Untrusted Foundry
    1319 -- 1324Esteban Garzón, Yosi Greenblatt, Odem Harel, Marco Lanuzza, Adam Teman. Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study
    1325 -- 1334Jinbo Chen, Chengcheng Lu, JiaCheng Ni, Xiaochen Guo, Patrick Girard 0001, Yuanqing Cheng. DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect
    1335 -- 1347Wei-pei Huang, Ray C. C. Cheung, Hong Yan 0001. An Efficient Parallel Processor for Dense Tensor Computation
    1348 -- 1359Deepak Dasalukunte, Richard Dorrance, Le Liang, Lu Lu 0002. A Vector Processor for Mean Field Bayesian Channel Estimation
    1360 -- 1369Mohsen Javadi, Hossein Miar Naimi, Saheed Tijani, Danilo Manstretta, Rinaldo Castello. A Highly Linear SAW-Less Noise-Canceling Receiver With Shared TIAs Architecture
    1370 -- 1378Xiuqin Chu, Wenting Guo, Jun Wang 0034, Feng Wu 0005, Yuhuan Luo, YuShan Li. Fast and Accurate Estimation of Statistical Eye Diagram for Nonlinear High-Speed Links
    1379 -- 1391Kuang-Wei Cheng, Shih-En Chen. An Ultralow-Power OOK/BFSK/DBPSK Wake-Up Receiver Based on Injection-Locked Oscillator
    1392 -- 1401Pierpaolo Palestri, Ahmed Elnaqib, Davide Menin, Klaid Shyti, Francesco Brandonisio, Andrea Bandiziol, Davide Rossi, Roberto Nonis. Analytical Modeling of Jitter in Bang-Bang CDR Circuits Featuring Phase Interpolation
    1402 -- 1415Pedro Tauã Lopes Pereira, Guilherme Paim, Patrícia Ücker Leleu da Costa, Eduardo Antônio César da Costa, Sérgio Jose Melo de Almeida, Sergio Bampi. Architectural Exploration for Energy-Efficient Fixed-Point Kalman Filter VLSI Design
    1416 -- 1427Meng Ni, Xiao Wang 0021, Fule Li, Zhihua Wang 0001. A 13-bit 312.5-MS/s Pipelined SAR ADC With Open-Loop Integrator-Based Residue Amplifier and Gain-Stabilized Integration Time Generation
    1428 -- 1436Jiann-Jong Chen, Yuh-Shyan Hwang, Jyun-Heng Wu, Chien-Hung Lai, Yi-Tsen Ku. A New Improved V-Square-Controlled Buck Converter With Rail-to-Rail OTA-Based Current-Sensing Circuits
    1437 -- 1450Jeongwoo Heo, Taewhan Kim. Reusable Delay Path Synthesis for Lightening Asynchronous Pipeline Controller
    1451 -- 1464Pampa Howladar, Pranab Roy, Hafizur Rahaman 0001. Droplet Transportation in MEDA-Based Biochips: An Enhanced Technique for Intelligent Cross-Contamination Avoidance
    1465 -- 1469Rituparna Choudhury, Shaik Rafi Ahamed, Prithwijit Guha. Training Accelerator for Two Means Decision Tree
    1470 -- 1474Fei Lyu 0002, Zhelong Mao, Jin Zhang, Yu Wang, Yuanyong Luo. PWL-Based Architecture for the Logarithmic Computation of Floating-Point Numbers
    1475 -- 1479Erik Larsson, Zehang Xiang, Prathamesh Murali. Graceful Degradation of Reconfigurable Scan Networks
    1480 -- 1484Yangtao Dong, Chirn Chye Boon, Xin Ding 0003, Chenyang Li, Zhe Liu. A Bidirectional Nonlinearly Coupled QVCO With Passive Phase Interpolation for Multiphase Signals Generation
    1485 -- 1489Haoyu Zhuang, Wenzhen Cao, Xizhu Peng, He Tang. A Three-Stage Comparator and Its Modified Version With Fast Speed and Low Kickback
    1490 -- 1494Gyanendra Singh, Samba Raju Chiluveru, Balasubramanian Raman, Manoj Tripathy, Brajesh Kumar Kaushik. Novel Architecture for Lifting Discrete Wavelet Packet Transform With Arbitrary Tree Structure
    1495 -- 1499Yoshisato Yokoyama, Yuichiro Ishii, Koji Nii, Kazutoshi Kobayashi. Cost-Effective Test Screening Method on 40-nm Embedded SRAMs for Low-Power MCUs
    1500 -- 1504Irith Pomeranz. Functional Constraints in the Selection of Two-Cycle Gate-Exhaustive Faults for Test Generation

    Volume 29, Issue 6

    1039 -- 1051Kamlesh Singh, Barry de Bruin, Hailong Jiao, Jos Huisken, Henk Corporaal, José Pineda de Gyvez. Converter-Free Power Delivery Using Voltage Stacking for Near/Subthreshold Operation
    1052 -- 1060Yin Sun, JongJoo Lee, Chulsoon Hwang. A Generalized Power Supply Induced Jitter Model Based on Power Supply Rejection Ratio Response
    1061 -- 1072Ruzica Jevtic, Marko Ylitolva, Clara Calonge, Martti Ojanen, Tero Säntti, Lauri Koskinen. EM Side-Channel Countermeasure for Switched-Capacitor DC-DC Converters Based on Amplitude Modulation
    1073 -- 1082Zhen Gao, Lingling Zhang, Yinghao Cheng, Kangkang Guo, Anees Ullah, Pedro Reviriego. Design of FPGA-Implemented Reed-Solomon Erasure Code (RS-EC) Decoders With Fault Detection and Location on User Memory
    1083 -- 1094Dongyun Kam, Hoyoung Yoo, Youngjoo Lee. Ultralow-Latency Successive Cancellation Polar Decoding Architecture Using Tree-Level Parallelism
    1095 -- 1107Zhuojun Chen, Judi Zhang, Shuangchun Wen, Ya Li, Qinghui Hong. Competitive Neural Network Circuit Based on Winner-Take-All Mechanism and Online Hebbian Learning Rule
    1108 -- 1121John Reuben, Stefan Pechmann. Accelerated Addition in Resistive RAM Array Using Parallel-Friendly Majority Gates
    1122 -- 1131Pablo Ilha Vaz, Patrick Girard 0001, Arnaud Virazel, Hassen Aziza. Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout Transistors
    1132 -- 1140Firat Celik, Ayca Akkaya, Armin Tajalli, Yusuf Leblebici. A 32-Gb/s PAM-4 SST Transmitter With Four-Tap FFE Using High-Impedance Driver in 28-nm FDSOI
    1141 -- 1151Jérémy Nadal, Amer Baghdadi. Parallel and Flexible 5G LDPC Decoder Architecture Targeting FPGA
    1152 -- 1163Lingjun Zhu, Lennart Bamberg, Sai Surya Kiran Pentapati, Kyungwook Chang, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Brian Cline, Saurabh Sinha, Xiaoqing Xu, Alberto García Ortiz, Sung Kyu Lim. High-Performance Logic-on-Memory Monolithic 3-D IC Designs for Arm Cortex-A Processors
    1164 -- 1177Jungil Mok, Hyeonchan Lim, Sungho Kang. Enhanced Postbond Test Architecture for Bridge Defects Between the TSVs
    1178 -- 1191Chung-Kuan Cheng, Chia-Tung Ho, Daeyeal Lee, Bill Lin, Dongwon Park. Complementary-FET (CFET) Standard Cell Synthesis Framework for Design and System Technology Co-Optimization Using SMT
    1192 -- 1205Suchang Kim, Seungho Na, Byeong Yong Kong, Jaewoong Choi, In-Cheol Park. Real-Time SSDLite Object Detection on FPGA
    1206 -- 1219Febin P. Sunny, Asif Mirza, Ishan G. Thakkar, Mahdi Nikdast, Sudeep Pasricha. ARXON: A Framework for Approximate Communication Over Photonic Networks-on-Chip
    1220 -- 1230Wenbo Guo 0009, Shuguo Li. Fast Binary Counters and Compressors Generated by Sorting Network
    1231 -- 1243Tanfer Alan, Andreas Gerstlauer, Jörg Henkel. Cross-Layer Approximate Hardware Synthesis for Runtime Configurable Accuracy
    1244 -- 1256I-Ju Wang, Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang 0001, Bo-Jun Chen, Hsin-Wen Wei, Wei Kuan Shih. Enabling Write-Reduction Multiversion Scheme With Efficient Dual-Range Query Over NVRAM
    1257 -- 1270Jin-Tai Yan. Via-Minimization-Oriented Region Routing Under Length-Matching Constraints in Rapid Single-Flux-Quantum Circuits
    1271 -- 1284Guilherme Cardoso Medeiros, Moritz Fieback, Lizhou Wu, Mottaqiallah Taouil, Letícia Maria Bolzani Poehls, Said Hamdioui. Hard-to-Detect Fault Analysis in FinFET SRAMs

    Volume 29, Issue 5

    815 -- 842Massimo Alioto. Second Quarter of the 2021 Editorial Year - A Year in Crescendo
    843 -- 856Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal 0001, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim. Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities
    857 -- 870Rui Zhang 0048, Kexin Yang, Zhaocheng Liu, Taizhi Liu, Wenshan Cai, Linda Milor. A Comprehensive Framework for Analysis of Time-Dependent Performance-Reliability Degradation of SRAM Cache Memory
    871 -- 882Azad Mahmoudi, Pooya Torkzadeh, Massoud Dousti. A 6-Bit 1.5-GS/s SAR ADC With Smart Speculative Two-Tap Embedded DFE in 130-nm CMOS for Wireline Receiver Applications
    883 -- 894Ching-Yuan Yang, Miao-Shan Li, Ai-Jia Chuang. A Wide-Range Folded-Tuned Dual-DLL-Based Clock-Deskewing Circuit for Core-to-Core Links
    895 -- 903Jian Liu, Shubin Liu, Ruixue Ding, Zhangming Zhu. A Conversion Mode Reconfigurable SAR ADC for Multistandard Systems
    904 -- 915Hsun-Wei Chan, Wei-Che Lee, Kang-Lun Chiu, Chih-Wei Jen, Shyh-Jye Jou. A Digital Two-Stage Phase Noise Compensation and rCFO/rSCO Tracking Module for mmW Single Carrier Systems
    916 -- 924Abdolah Amirany, Kian Jafari, Mohammad Hossein Moaiyeri. High-Performance Spintronic Nonvolatile Ternary Flip-Flop and Universal Shift Register
    925 -- 935Nima Taherinejad. SIXOR: Single-Cycle In-Memristor XOR
    936 -- 949Di Wu, Xitian Fan, Wei Cao 0002, Lingli Wang. SWM: A High-Performance Sparse-Winograd Matrix Multiplication CNN Accelerator
    950 -- 961Fatima Hameed Khan, Wala Saadeh. An EEG-Based Hypnotic State Monitor for Patients During General Anesthesia
    962 -- 972Dimitrios Garyfallou, Stavros Simoglou, Nikolaos Sketopoulos, Charalampos Antoniadis, Christos P. Sotiriou, Nestor E. Evmorfopoulos, George I. Stamoulis. Gate Delay Estimation With Library Compatible Current Source Models and Effective Capacitance
    973 -- 984Jai-Ming Lin, You-Lun Deng, Ya Chu Yang, Jia-Jian Chen, Po-Chen Lu. Dataflow-Aware Macro Placement Based on Simulated Evolution Algorithm for Mixed-Size Designs
    985 -- 997Jai-Ming Lin, Tai-Ting Chen, Hao-Yuan Hsieh, Ya-Ting Shyu, Yeong-Jar Chang, Juin-Ming Lu. Thermal-Aware Fixed-Outline Floorplanning Using Analytical Models With Thermal-Force Modulation
    998 -- 1008Francesco Centurelli, Giuseppe Scotti, Gaetano Palumbo. A Very-Low-Voltage Frequency Divider in Folded MOS Current Mode Logic With Complementary n- and p-type Flip-Flops
    1009 -- 1021Biswajit Bhowmik. Dugdugi: An Optimal Fault Addressing Scheme for Octagon-Like On-Chip Communication Networks
    1022 -- 1032Heng You, Jia Yuan, Zenghui Yu, Shushan Qiao. Low-Power Retentive True Single-Phase-Clocked Flip-Flop With Redundant-Precharge-Free Operation
    1033 -- 1037Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh. m)

    Volume 29, Issue 4

    591 -- 604Andrew B. Kahng, Seokhyeong Kang, Seungwon Kim, Bangqi Xu. Enhanced Power Delivery Pathfinding for Emerging 3-D Integration Technology
    605 -- 616Gauthaman Murali, Heechun Park, Eric Qin 0001, Hakki Mert Torun, Majid Ahadi Dolatsara, Madhavan Swaminathan, Tushar Krishna, Sung Kyu Lim. Clock Delivery Network Design and Analysis for Interposer-Based 2.5-D Heterogeneous Systems
    617 -- 630Hongbo Cao, Faqiang Wang. Spreading Operation Frequency Ranges of Memristor Emulators via a New Sine-Based Method
    631 -- 642Kwang-Woo Lee, Hyun Kook Park, Seong-Ook Jung. Adaptive Sensing Voltage Modulation Technique in Cross-Point OTS-PRAM
    643 -- 656Kimia Zamiri Azar, Hadi Mardani Kamali, Shervin Roshanisefat, Houman Homayoun, Christos P. Sotiriou, Avesta Sasan. Data Flow Obfuscation: A New Paradigm for Obfuscating Circuits
    657 -- 666Paulo Realpe-Muñoz, Jaime Velasco-Medina, Guillermo Adolfo-David. m)
    667 -- 676Moslem Heidarpur, Mitra Mirhassani. An Efficient and High-Speed Overlap-Free Karatsuba-Based Finite-Field Multiplier for FGPA Implementation
    677 -- 690Pasquale Davide Schiavone, Davide Rossi, Alfio Di Mauro, Frank K. Gürkaynak, Timothy Saxe, Mao Wang, Ket Chong Yap, Luca Benini. Arnold: An eFPGA-Augmented RISC-V SoC for Flexible and Low-Power IoT End Nodes
    691 -- 701Saambhavi Baskaran, Jack Sampson. Evaluation of Tradeoffs in the Design of FPGA Fabrics Using Electrostrictive 2-D FETs
    702 -- 715Rachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001. ROMANet: Fine-Grained Reuse-Driven Off-Chip Memory Access Management and Data Organization for Deep Neural Network Accelerators
    716 -- 729Alberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique 0001. FEECA: Design Space Exploration for Low-Latency and Energy-Efficient Capsule Network Accelerators
    730 -- 738Sourjya Roy, Shrihari Sridharan, Shubham Jain, Anand Raghunathan. TxSim: Modeling Training of Deep Neural Networks on Resistive Crossbar Systems
    739 -- 746Sanghun Lee, Kisang Jung, Hak Seong Kim, Huan Nguyen 0005, Thinh Nguyen, Luan Nguyen, Cuong Huynh, Kunhee Cho, Jusung Kim. Frequency-Locked RF Power Oscillator With 43-dBm Output Power and 58% Efficiency
    747 -- 759Shahriar Shahabuddin, Ilkka Hautala, Markku J. Juntti, Christoph Studer. ADMM-Based Infinity-Norm Detection for Massive MIMO: Algorithm and VLSI Architecture
    760 -- 773Rohit B. Chaurasiya, Rahul Shrestha. A New Hardware-Efficient Spectrum-Sensor VLSI Architecture for Data-Fusion-Based Cooperative Cognitive-Radio Network
    774 -- 787Stefan Mach, Fabian Schuiki, Florian Zaruba, Luca Benini. FPnew: An Open-Source Multiformat Floating-Point Unit Architecture for Energy-Proportional Transprecision Computing
    788 -- 799Yu-Hsuan Lee, Tzu-Chieh Chen, Hsuan-Chi Liang, Jian-Xiang Liao. Algorithm and Architecture Design of FAST-C Image Corner Detection Engine
    800 -- 813Mahmoud Masadeh, Osman Hasan, Sofiène Tahar. Machine-Learning-Based Self-Tunable Design of Approximate Computing

    Volume 29, Issue 3

    447 -- 460Hasan Erdem Yantir, Ahmed M. Eltawil, Khaled N. Salama. IMCA: An Efficient In-Memory Convolution Accelerator
    461 -- 471Steven Colleman, Marian Verhelst. High-Utilization, High-Flexibility Depth-First CNN Coprocessor for Image Pixel Processing on FPGA
    472 -- 484Dawen Xu 0002, Ziyang Zhu, Cheng Liu, Ying Wang 0001, Shuang Zhao, Lei Zhang 0008, Huaguo Liang, Huawei Li, Kwang-Ting Cheng. Reliability Evaluation and Analysis of FPGA-Based Neural Network Acceleration System
    485 -- 498Shamik Kundu, Suvadeep Banerjee, Arnab Raha, Suriyaprakash Natarajan, Kanad Basu. Toward Functional Safety of Systolic Array-Based Deep Learning Hardware Accelerators
    499 -- 511Taehwan Kim 0007, Heechun Park, Taewhan Kim. Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady-State- Driven Approach
    512 -- 518Isaak Yang, Kwang-Hyun Cho. A Low-Power Timing-Error-Tolerant Circuit by Controlling a Clock
    519 -- 529Yi-Wen Hung, Yung-Chih Chen, Chi Lo, Austin Go So, Shih-Chieh Chang. Dynamic Workload Allocation for Edge Computing
    530 -- 543Mengting Yan, Haoran Wei, Marvin Onabajo. On-Chip Thermal Profiling to Detect Malicious Activity: System-Level Concepts and Design of Key Building Blocks
    544 -- 557Chris Nigh, Alex Orailoglu. AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction
    558 -- 567Yuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini. SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing
    568 -- 579Chenxi Zhao, Jiawei Guo, Huihua Liu, Yiming Yu, Yunqiu Wu, Kai Kang. A 33-41-GHz SiGe-BiCMOS Digital Step Attenuator With Minimized Unit Impedance Variation
    580 -- 590Charalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis. Graph-Based Sparsification and Synthesis of Dense Matrices in the Reduction of RLC Circuits

    Volume 29, Issue 2

    247 -- 258Seyfeddine Boukhtache, Benoît Blaysat, Michel Grédiac, François Berry. Alternatives to Bicubic Interpolation Considering FPGA Hardware Resource Consumption
    259 -- 272Jun Li, Paul Chow, Yuanxi Peng, Tian Jiang. FPGA Implementation of an Improved OMP for Compressive Sensing Reconstruction
    273 -- 286Karim Hammad, Zhongpan Wu, Ebrahim Ghafar-Zadeh, Sebastian Magierowski. A Scalable Hardware Accelerator for Mobile DNA Sequencing
    287 -- 296Chenbing Qu, Zhangming Zhu, Yunfei En, Liwei Wang 0003, Xiaoxian Liu. Area-Efficient Extended 3-D Inductor Based on TSV Technology for RF Applications
    297 -- 306Atul Thakur, Shouri Chatterjee. A 4.4-mA ESD-Safe 900-MHz LNA With 0.9-dB Noise Figure
    307 -- 320Zhuojun Liang, Dongxu Lv, Chao Cui, Hai-Bao Chen, Weifeng He, Weiguang Sheng, Naifeng Jing, Zhigang Mao, Guanghui He. A 3.85-Gb/s 8 × 8 Soft-Output MIMO Detector With Lattice-Reduction-Aided Channel Preprocessing
    321 -- 332Tsutomu Yoshimura. Study of Injection Pulling of Oscillators in Phase-Locked Loops
    333 -- 346Jian Zhou 0012, Sumit K. Mandal, Brendan L. West, Siyuan Wei, Ümit Y. Ogras, Oliver D. Kripfgans, J. Brian Fowlkes, Thomas F. Wenisch, Chaitali Chakrabarti. Front-End Architecture Design for Low-Complexity 3-D Ultrasound Imaging Based on Synthetic Aperture Sequential Beamforming
    347 -- 358Kai Wang, Fengkai Yuan, Lutan Zhao, Rui Hou, Zhenzhou Ji, Dan Meng. Mitigating Cross-Core Cache Attacks via Suspicious Traffic Detection
    359 -- 371Jing Tian 0004, Jun Lin, Zhongfeng Wang. Fast Modular Multipliers for Supersingular Isogeny-Based Post-Quantum Cryptography
    372 -- 385Riduan Khaddam-Aljameh, Pier Andrea Francese, Luca Benini, Evangelos Eleftheriou. An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power
    386 -- 396Gauthaman Murali, Xiaoyu Sun, Shimeng Yu, Sung Kyu Lim. Heterogeneous Mixed-Signal Monolithic 3-D In-Memory Computing Using Resistive RAM
    397 -- 408Daehan Ji, Dongyeob Shin, Jongsun Park 0001. An Error Compensation Technique for Low-Voltage DNN Accelerators
    409 -- 422Sanmitra Banerjee, Arjun Chaudhuri, August Ning, Krishnendu Chakrabarty. Variation-Aware Delay Fault Testing for Carbon-Nanotube FET Circuits
    423 -- 433Irith Pomeranz, Xijiang Lin. Single Test Type to Replace Broadside and Skewed-Load Tests for Transition Faults
    434 -- 446Roohollah Yarmand, Mehdi Kamal, Ali Afzali-Kusha, Pooria Esmaeli, Massoud Pedram. OPTIMA: An Approach for Online Management of Cache Approximation Levels in Approximate Processing Systems

    Volume 29, Issue 12

    2013 -- 2026Vaibhav Venugopal Rao, Ioannis Savidis. Performance and Security Analysis of Parameter-Obfuscated Analog Circuits
    2027 -- 2039Shanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu. Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR Encryption
    2040 -- 2051Sina Sayyah Ensan, Karthikeyan Nagarajan, Mohammad Nasim Imtiaz Khan, Swaroop Ghosh. SCARE: Side Channel Attack on In-Memory Computing for Reverse Engineering
    2052 -- 2063Soner Seçkiner, Selçuk Köse. Preprocessing of the Physical Leakage Information to Combine Side-Channel Distinguishers
    2064 -- 2075Turki Alnuayri, S. Saqib Khursheed, Antonio Leonel Hernández Martínez, Daniele Rossi 0001. Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs
    2076 -- 2085Sandeep Kumar, Atin Mukherjee 0001. A Highly Robust and Low-Power Real-Time Double Node Upset Self-Healing Latch for Radiation-Prone Applications
    2086 -- 2097Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim. A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses
    2098 -- 2109Jaewon Choi, Nam-Seog Kim. A Spurious and Oscillator Pulling Free CMOS Quadrature LO-Generator for Cellular NB-IoT
    2110 -- 2118Juncheng Wang, XueFeng Chen, Rui Bai, Patrick Yin Chiang, Quan Pan. A 4 × 10 Gb/s Adaptive Optical Receiver Utilizing Current-Reuse and Crosstalk-Remove
    2119 -- 2129Zakaria El Alaoui Ismaili, Wessam Ajib, Frederic Nabki, François Gagnon. A 0.1-9-GHz Frequency Synthesizer for Avionic SDR Applications in 0.13-μm CMOS Technology
    2130 -- 2142Mohamed Elshamy, Alhassan Sayed, Marie-Minerve Louërat, Hassan Aboushady, Haralampos-G. Stratigopoulos. Locking by Untuning: A Lock-Less Approach for Analog and Mixed-Signal IC Security
    2143 -- 2152Kentaro Yoshioka. VCO-Based Comparator: A Fully Adaptive Noise Scaling Comparator for High-Precision and Low-Power SAR ADCs
    2153 -- 2162Zule Xu, Naoki Ojima, Shuowei Li, Tetsuya Iizuka. An All-Standard-Cell-Based Synthesizable SAR ADC With Nonlinearity-Compensated RDAC
    2163 -- 2171Islam Mansour, Marwa Mansour, Mohamed Aboualalaa, Ahmed Allam, Adel B. Abdel-Rahman, Ramesh K. Pokharel, Mohammed Abo-Zahhad. A Multiband VCO Using a Switched Series Resonance for Fine Frequency Tuning Sensitivity and Phase Noise Improvement
    2172 -- 2185Chua-Chin Wang, Lean Karlo S. Tolentino, Chia-Yi Huang, Chia-Hung Yeh. A 40-nm CMOS Multifunctional Computing-in-Memory (CIM) Using Single-Ended Disturb-Free 7T 1-Kb SRAM
    2186 -- 2196Nicholas Jao, Akshay Krishna Ramanathan, John Sampson, Vijaykrishnan Narayanan. Sparse Vector-Matrix Multiplication Acceleration in Diode-Selected Crossbars
    2197 -- 2209Ming Ling, Qingde Lin, Ke Tan, Tianxiang Shao, Shan Shen, Jun Yang 0006. A Design of Timing Speculation SRAM-Based L1 Caches With PVT Autotracking Under Near-Threshold Voltages
    2210 -- 2219Xinyu Du, Lidan Wang, Dengwei Yan, Shukai Duan. A Multiring Julia Fractal Chaotic System With Separated-Scroll Attractors
    2220 -- 2228Juan Sebastian P. Giraldo, Vikram Jain, Marian Verhelst. Efficient Execution of Temporal Convolutional Networks for Embedded Keyword Spotting

    Volume 29, Issue 11

    1813 -- 1823Nikos Temenos, Paul P. Sotiriadis. Stochastic Computing Max & Min Architectures Using Markov Chains: Design, Analysis, and Implementation
    1824 -- 1837Zhenxin Zhao, Lihong Zhang. Efficient Performance Modeling for Automated CMOS Analog Circuit Synthesis
    1838 -- 1849Po-Hsuan Wei, Boris Murmann. Analog and Mixed-Signal Layout Automation Using Digital Place-and-Route Tools
    1850 -- 1860Mohamed B. Elamien, Brent J. Maundy, Leonid Belostotski, Ahmed S. Elwakil. Analog Circuit Design Using Symbolic Math Toolboxes: Demonstrative Examples
    1861 -- 1874Ahmed S. Emara, Denis Romanov, Gordon W. Roberts, Sadok Aouini, Soheyl Ziabakhsh, Mahdi Parvizi, Naim Ben Hamida. An Area-Efficient High-Resolution Segmented ΣΔ-DAC for Built-In Self-Test Applications
    1875 -- 1888Shao-Chun Hung, Yi-Chen Lu, Sung Kyu Lim, Krishnendu Chakrabarty. Power Supply Noise-Aware At-Speed Delay Fault Testing of Monolithic 3-D ICs
    1889 -- 1902Jin-Tai Yan. Via-Avoidance-Oriented Interposer Routing for Layer Minimization in 2.5-D IC Designs
    1903 -- 1911Qianqian Wang, Fei Liu, Cece Huang, Qianhui Li, Zongliang Huo. A Small Ripple and High-Efficiency Wordline Voltage Generator for 3-D nand Flash Memories
    1912 -- 1921Madhan Thirumoorthi, Marko Jovanovic, Mitra Mirhassani, Mohammed A. S. Khalid. Design and Evaluation of a Hybrid Chaotic-Bistable Ring PUF
    1922 -- 1929Yingchun Lu, Xinyu Wang, Yanjie Wang, Yuan Zhang, Liang Yao, Maoxiang Yi, Zhengfeng Huang, Huaguo Liang. Pure Digital Scalable Mixed Entropy Separation Structure for Physical Unclonable Function and True Random Number Generator
    1930 -- 1942Abdullah Aljuffri, Marc Zwalua, Cezar Rodolfo Wedig Reinbrecht, Said Hamdioui, Mottaqiallah Taouil. Applying Thermal Side-Channel Attacks on Asymmetric Cryptography
    1943 -- 1954Milad Bahadori, Kimmo Järvinen 0001, Valtteri Niemi. FPGA Implementations of 256-Bit SNOW Stream Ciphers for Postquantum Mobile Security
    1955 -- 1966Dawen Xu 0002, Meng He 0012, Cheng Liu 0008, Ying Wang 0001, Long Cheng 0003, Huawei Li, Xiaowei Li 0001, Kwang-Ting Cheng. R2F: A Remote Retraining Framework for AIoT Processors With Computing Errors
    1967 -- 1980Libo Chang, Shengbing Zhang, Huimin Du, Yue Chen, Shiyu Wang. A Reconfigurable Neural Network Processor With Tile-Grained Multicore Pipeline for Object Detection on FPGA
    1981 -- 1993Hongtao Zhong, Shengjie Cao, Li Jiang 0002, Xia An, Vijaykrishnan Narayanan, Yongpan Liu, Huazhong Yang, Xueqing Li. DyTAN: Dynamic Ternary Content Addressable Memory Using Nanoelectromechanical Relays
    1994 -- 1997Neelam Arya, Manisha Pattanaik, G. K. Sharma 0001. Energy-Efficient Logarithmic Square Rooter for Error-Resilient Applications
    1998 -- 2002Heiner Bauer, Sebastian Höppner, Chris Paul Iatrou, Zohra Charania, Stephan Hartmann 0002, Saif-Ur Rehman, Andreas Dixius, Georg Ellguth, Dennis Walter, Johannes Uhlig, Felix Neumärker, Marc Berthel, Marco Stolba, Florian Kelber, Leon Urbas, Christian Mayr. Hardware Implementation of an OPC UA Server for Industrial Field Devices
    2003 -- 2007Chenggang Yan, Jie Sun, Weiqiang Liu. An Efficient High SFDR PDDS Using High-Pass-Shaped Phase Dithering
    2008 -- 2012Yongwoon Song, Jooyoung Hwang, Insoon Jo, Hyukjun Lee. Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory

    Volume 29, Issue 10

    1685 -- 1692Na Niu, Fangfa Fu, Bing Yang, Qiang Wang, Xinpeng Li, Fengchang Lai, Jinxiang Wang. PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems
    1693 -- 1706Hritom Das, Ali Ahmad Haidous, Scott C. Smith, Na Gong. Flexible Low-Cost Power-Efficient Video Memory With ECC-Adaptation
    1707 -- 1719M. Sultan M. Siddiqui, Zhao Chuan Lee, Tony Tae-Hyoung Kim. A 16-kb 9T Ultralow-Voltage SRAM With Column-Based Split Cell-VSS, Data-Aware Write-Assist, and Enhanced Read Sensing Margin in 28-nm FDSOI
    1720 -- 1729Chih-Wei Tsai, Yu-Ting Chiu, Yo-Hao Tu, Kuo-Hsing Cheng. A Wide-Range All-Digital Delay-Locked Loop for DDR1-DDR5 Applications
    1730 -- 1742Kaniz Mishty, Mehdi Sadi. Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM
    1743 -- 1756Aqeeb Iqbal Arka, Biresh Kumar Joardar, Janardhan Rao Doppa, Partha Pratim Pande, Krishnendu Chakrabarty. Performance and Accuracy Tradeoffs for Training Graph Neural Networks on ReRAM-Based Architectures
    1757 -- 1770Morteza Hosseini, Nitheesh Kumar Manjunath, Bharat Prakash, Arnab Neelim Mazumder, Vandana Chandrareddy, Houman Homayoun, Tinoosh Mohsenin. Cyclic Sparsely Connected Architectures for Compact Deep Convolutional Neural Networks
    1771 -- 1781Tianqi Kong, Shuguo Li. Design and Analysis of Approximate 4-2 Compressors for High-Accuracy Multipliers
    1782 -- 1789Bin Zhou, Guangsen Wang, Guisheng Jie, Qing Liu, Zhiwei Wang. A High-Speed Floating-Point Multiply-Accumulator Based on FPGAs
    1790 -- 1799Noel Daniel Gundi, Tahmoures Shabanian, Prabal Basu, Pramesh Pandey, Sanghamitra Roy, Koushik Chakraborty. EFFORT: A Comprehensive Technique to Tackle Timing Violations and Improve Energy Efficiency of Near-Threshold Tensor Processing Units
    1800 -- 1811Hayate Okuhara, Ahmed Elnaqib, Martino Dazzi, Pierpaolo Palestri, Simone Benatti, Luca Benini, Davide Rossi. A Fully Integrated 5-mW, 0.8-Gbps Energy-Efficient Chip-to-Chip Data Link for Ultralow-Power IoT End-Nodes in 65-nm CMOS

    Volume 29, Issue 1

    1 -- 2Massimo Alioto. Opening of the 2021 Editorial Year - Overture for a New Year of Change
    3 -- 13Boris Murmann. Mixed-Signal Computing for Deep Neural Network Inference
    14 -- 23M. Imtiaz Rashid, Farah Ferdaus, Bashir M. Sabquat Bahar Talukder, Paul Henny, Aubrey N. Beal, Md. Tauhidur Rahman. True Random Number Generation Using Latency Variations of FRAM
    24 -- 37Nadesh Ramanathan, George A. Constantinides, John Wickerson. Global Analysis of C Concurrency in High-Level Synthesis
    38 -- 50Nadir Khan, Jorge Castro-Godínez, Shixiang Xue, Jörg Henkel, Jürgen Becker 0001. Automatic Floorplanning and Standalone Generation of Bitstream-Level IP Cores
    51 -- 64Ahmed Mahdi, Nikos Kanistras, Vassilis Paliouras. A Multirate Fully Parallel LDPC Encoder for the IEEE 802.11n/ac/ax QC-LDPC Codes Based on Reduced Complexity XOR Trees
    65 -- 75Rahul Shrestha. A Multiple-Radix MAP-Decoder Microarchitecture and Its ASIC Implementation for Energy-Efficient and Variable-Throughput Applications
    76 -- 88Nilanjan Mukherjee 0001, Daniel Tille, Mahendar Sapati, Yingdi Liu, Jeffrey Mayer, Sylwester Milewski, Elham K. Moghaddam, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer. Time and Area Optimized Testing of Automotive ICs
    89 -- 99Irith Pomeranz. Partitioning Functional Test Sequences Into Multicycle Functional Broadside Tests
    100 -- 111Gang Li, Pengjun Wang, Xuejiao Ma, Yijian Shi, Bo Chen, Yuejun Zhang. A Multimode Configurable Physically Unclonable Function With Bit-Instability-Screening and Power-Gating Strategies
    112 -- 123Anirban Sengupta, Mahendra Rathor. Facial Biometric for Securing Hardware Accelerators
    124 -- 135Tiancheng Yang, Ankit Mittal, Yunsi Fei, Aatmesh Shrivastava. Large Delay Analog Trojans: A Silent Fabrication-Time Attack Exploiting Analog Modalities
    136 -- 148Karim Shahbazi, Seok-Bum Ko. Area-Efficient Nano-AES Implementation for Internet-of-Things Devices
    149 -- 161Fengchao Zhang, Shubhra Deb Paul, Patanjali SLPSK, Amit Ranjan Trivedi, Swarup Bhunia. On Database-Free Authentication of Microelectronic Components
    162 -- 175Seongsik Park, Jaehee Jang, Sei Joon Kim, Byunggook Na, Sungroh Yoon. Memory-Augmented Neural Networks on FPGA for Real-Time and Energy-Efficient Question Answering
    176 -- 188Kun-Chih Chen, Ya-Wei Huang, Geng-Ming Liu, Jing-Wen Liang, Yueh-Chi Yang, Yuan-Hao Liao. A Hierarchical K-Means-Assisted Scenario-Aware Reconfigurable Convolutional Neural Network
    189 -- 202Qingkun Chen, Wenjin Huang, Yuanshan Zhang, Yihua Huang. An IP Core Mapping Algorithm Based on Neural Networks
    203 -- 214Vishnu Unnikrishnan, Okko Järvinen, Waqas Siddiqui, Kari Stadius, Marko Kosunen, Jussi Ryynänen. Data Conversion With Subgate-Delay Time Resolution Using Cyclic-Coupled Ring Oscillators
    215 -- 226Anirban Chakraborty, Ayan Banerjee. CORDIC-Based High-Speed VLSI Architecture of Transform Model Estimation for Real-Time Imaging
    227 -- 231Qihui Zhang, Ning Ning, Jing Li, Qi Yu 0002, Kejun Wu, Zhong Zhang 0002. A Second-Order Noise-Shaping SAR ADC Using Two Passive Integrators Separated by the Comparator
    232 -- 236Alvaro Cintas Canto, Mehran Mozaffari Kermani, Reza Azarderakhsh. Reliable CRC-Based Error Detection Constructions for Finite Field Multipliers With Applications in Cryptography
    237 -- 241Sina Sayyah Ensan, Swaroop Ghosh. ReLOPE: Resistive RAM-Based Linear First-Order Partial Differential Equation Solver
    242 -- 246Irith Pomeranz. Test Compaction by Backward and Forward Extension of Multicycle Tests
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