External Links

    Journal: VLSI Design

    Volume 1, Issue 4

    0 -- 0Rochit Rajsuman. Special Issue on Digital Hardware Testing
    261 -- 276Michael Ogbonna Esonu, Dhamin Al-Khalili, Côme Rozon. Fault Characterization and Testability Analysis of Emitter Coupled Logic and Comparison with CMOS & BiCMOS Circuits
    277 -- 284Yashwant K. Malaiya, Anura P. Jayasumana, Carol Q. Tong, Sankaran M. Menon. DDQ Testing for Large ICs
    285 -- 298Michael J. Batek, John P. Hayes. Optimal Testing and Design of Adders
    299 -- 311Ben Mathew, Daniel G. Saab. Partial Reset: An Alternative DFT Approach
    313 -- 326Warren H. Debany Jr., Mark Gorniak, Anthony R. Macera, Daniel Daskiewich, Kevin A. Kwiat, Heather B. Dussault. Empirical Bounds on Fault Coverage Loss Due to LFSR Aliasing
    327 -- 334Rochit Rajsuman, Kamal Rajkanan. STD Architecture: A Practical Approach to Test M-Bits Random Access Memories
    335 -- 343Fadi Busaba, Parag K. Lala. An Approach for Self-Checking Realization of Interacting Finite State Machines
    345 -- 357Kevin T. Kornegay, Robert W. Brodersen. Integrated Test Solutions for a System Design Environment

    Volume 1, Issue 3

    181 -- 192Chien-In Henry Chen, Gerald E. Sobelman. Cluster Partitioning Techniques for Data Path Synthesis
    193 -- 215San-Yuan Wu, Sartaj Sahni. Fast Algorithms to Partition Simple Rectilinear Polygons
    217 -- 232Chien-In Henry Chen. Using PDM on Multiport Memory Allocation in Data Path
    233 -- 242Xiaoyu Song. An Optimum Channel Routing Algorithm in the Knock-knee Diagonal Model
    243 -- 259Inderpreet Bhasin, Joseph G. Tront. Block-Level Logic Extraction from CMOS VLSI Layouts

    Volume 1, Issue 2

    99 -- 111Marwan A. Jabri. Building Rectangular Floorplans-A Graph Theoretical Approach
    113 -- 126Sajjan G. Shiva, Judit U. Jones. A VHDL Based Expert System for Hardware Synthesis
    127 -- 154S. K. Nandy 0001, R. B. Panwar. Geometric Design Rule Check of VLSI Layouts in Mesh Connected Processors
    155 -- 167S. K. Nandy 0001. Geometric Design Rule Check of VLSI Layouts in Distributed Computing Environment
    169 -- 179Krishnamurthy Subramanian, Mehdi R. Zargham. Distributed and Parallel Demand Driven Logic Simulation Algorithms

    Volume 1, Issue 1

    0 -- 0. Editorial
    0 -- 0Sunil R. Das. Guest Editorial
    0 -- 0. About the Editor in Chief and the Guest Editor
    1 -- 7Earl E. Swartzlander Jr., Miroslaw Malek. Overlapped Subarray Segmentation: An Efficient Test Method for Cellular Arrays
    9 -- 22Rajiv Sharma, Kewal K. Saluja. Theory, Analysis and Implementation of an On-Line BIST Technique
    23 -- 44Jacob Savir, Paul H. Bardell. Built-In Self-Test: Milestones and Challenges
    45 -- 60Michael J. Bryan, Srinivas Devadas, Kurt Keutzer. Analysis and Design of Regular Structures for Robust Dynamic Fault Testability
    61 -- 70Walid A. Najjar, Pradip K. Srimani. Conditional Disconnection Probability in Star Graphs
    71 -- 85Warren H. Debany Jr.. Coverage of Node Shorts Using Internal Access and Equivalence Classes
    87 -- 97Samiha Mourad. Computer-Aided Testing Systems: Evaluation and Benchmark Circuits
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