| 75 | -- | 76 | Michael J. Schulte, Graham A. Jullien. Guest Editorial |
| 77 | -- | 89 | Ohsang Kwon, Kevin J. Nowka, Earl E. Swartzlander Jr.. A 16-Bit by 16-Bit MAC Design Using Fast 5: 3 Compressor Cells |
| 91 | -- | 100 | H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller. A New Algorithm for the Elimination of Common Subexpressions in Hardware Implementation of Digital Filters by Using Genetic Programming |
| 101 | -- | 116 | William L. Freking, Keshab K. Parhi. Performance-Scalable Array Architectures for Modular Multiplication |
| 117 | -- | 126 | Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll. Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality |
| 127 | -- | 142 | Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman. PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators |
| 143 | -- | 156 | Sridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang. Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers |
| 157 | -- | 171 | Mladen Berekovic, Peter Pirsch, Thorsten Selinger, Kai-Immo Wels, Carolina Miro, Anne Lafage, Christoph Heer, Giovanni Ghigo. Architecture of an Image Rendering Co-Processor for MPEG-4 Visual Compositing |
| 173 | -- | 184 | Wael M. Badawy, Magdy Bayoumi. A Multiplication-Free Algorithm and A Parallel Architecture for Affine Transformation |