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Ankur Agiwal, Montek Singh. Multi-Clock Latency-Insensitive Architecture and Wrapper Synthesis. Electronic Notes in Theoretical Computer Science, 146(2):5-28, 2006. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: An architecture and a wrapper synthesis approach for multi-clock latency-insensitive systemsAnkur Agiwal, Montek Singh. iccad 2005: 1006-1013 Generalized Latency-Insensitive Systems for Single-Clock and Multi-Clock ArchitecturesMontek Singh, Michael Theobald. date 2004: 1008-1013 [doi]
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