A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs - researchr publication authors

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Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi. A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs. J. Solid-State Circuits, 42(11):2611-2619, 2007. [doi]

This author has not been identified. Look up 'Kazutami Arimoto' in GoogleThis author has not been identified. Look up 'Fukashi Morishita' in GoogleThis author has not been identified. Look up 'Isamu Hayashi' in GoogleThis author has not been identified. Look up 'Katsumi Dosaka' in GoogleThis author has not been identified. Look up 'Hiroki Shimano' in GoogleThis author has not been identified. Look up 'Takashi Ipposhi' in Google

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