The following publications are possibly variants of this publication:
- Late Breaking Results: Heterogeneous Circuit Layout Centerline Extraction for Mask VerificationXiqiong Bai, Ziran Zhu, Peng Zou, Lichong Sun, Jianli Chen. dac 2021: 1364-1365 [doi]
- Concept and extraction method of ESD-critical parameters for function-based layout-level ESD protection circuit design verificationRouying Zhan, Haigang Feng, Qiong Wu, Xiaokang Guan, Guang Chen, Haolu Xie, Albert Z. Wang. aspdac 2004: 710-712 [doi]
- A knowledge-based program for compacting mask layout of integrated circuitsPei-Yung Hsiao, S. F. Steven Chen, Chia-Chun Tsai, Wu-Shiung Feng. cad, 23(3):223-231, 1991. [doi]