Synthesis of Sequential Circuits for Robust Path Delay Fault Testability - researchr publication related

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Sandeep Bhatia, Niraj K. Jha. Synthesis of Sequential Circuits for Robust Path Delay Fault Testability. In VLSI Design. pages 275-280, 1993.

The following publications are possibly variants of this publication:

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testabilitySteven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng. tcad, 16(12):1514-1521, 1997. [doi]

Synthesis of asynchronous circuits for stuck-at and robust path delay fault testabilitySteven M. Nowick, Niraj K. Jha, Fu-Chiung Cheng. vlsid 1995: 171-176 [doi]

Synthesis of Multi-Level Combinational Circuits for Complete Robust Path Delay Fault TestabilityNiraj K. Jha, Irith Pomeranz, Sudhakar M. Reddy, Robert J. Miller. ftcs 1992: 280-287

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