Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis

Ronn B. Brashear, Noel Menezes, Chanhee Oh, Lawrence T. Pillage, M. Ray Mercer. Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis. In Robert Werner, editor, EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France. pages 332-337, IEEE Computer Society, 1994.

@inproceedings{BrashearMOPM94,
  title = {Predicting Circuit Performance Using Circuit-level Statistical Timing Analysis},
  author = {Ronn B. Brashear and Noel Menezes and Chanhee Oh and Lawrence T. Pillage and M. Ray Mercer},
  year = {1994},
  tags = {analysis},
  researchr = {https://researchr.org/publication/BrashearMOPM94},
  cites = {0},
  citedby = {0},
  pages = {332-337},
  booktitle = {EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28 - March 3, 1994, Paris, France},
  editor = {Robert Werner},
  publisher = {IEEE Computer Society},
  isbn = {0-8186-5410-4},
}