Researchr is a web site for finding, collecting, sharing, and reviewing scientific publications, for researchers by researchers.
Sign up for an account to create a profile with publication list, tag and review your related work, and share bibliographies with your co-authors.
Chau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin. Combining technology mapping and placement for delay-minimization in FPGA designs. IEEE Trans. on CAD of Integrated Circuits and Systems, 14(9):1076-1084, 1995. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Combining technology mapping and placement for delay-optimization in FPGA designsChau-Shen Chen, Yu-Wen Tsay, TingTing Hwang, Allen C.-H. Wu, Youn-Long Lin. iccad 1993: 123-127 [doi] Simultaneous logic decomposition with technology mapping in FPGA designsGang Chen, Jason Cong. fpga 2001: 48-55 [doi] FPGA Technology Mapping with Adaptive Gate DecompositionLongfei Fan, Chang Wu. fpga 2023: 135-140 [doi]
The following publications are possibly variants of this publication: