The following publications are possibly variants of this publication:
- A fast-locking wide-range all-digital delay-locked loop with a starting SAR-bit prediction mechanismChia-Yu Yao, Yung-Hsiang Ho. vlsi-dat 2013: 1-4 [doi]
- A 40-550 MHz Harmonic-Free All-Digital Delay-Locked Loop Using a Variable SAR AlgorithmRong-Jyi Yang, Shen-Iuan Liu. jssc, 42(2):361-373, 2007. [doi]
- A Fast-Acquisition All-Digital Delay-Locked Loop Using a Starting-Bit Prediction Algorithm for the Successive-Approximation RegisterYung-Hsiang Ho, Chia-Yu Yao. tvlsi, 24(2):759-763, 2016. [doi]
- Designing a SAR-Based All-Digital Delay-Locked Loop With Constant Acquisition Cycles Using a Resettable Delay LineChia-Yu Yao, Yung-Hsiang Ho, Yi-Yao Chiu, Rong-Jyi Yang. tvlsi, 23(3):567-574, 2015. [doi]