Chen-Huan Chiang, Sandeep K. Gupta. BIST TPG for Combinational Cluster Interconnect Testing at Board Level. J. Electronic Testing, 16(5):427-442, 2000. [doi]
@article{ChiangG00,
title = {BIST TPG for Combinational Cluster Interconnect Testing at Board Level},
author = {Chen-Huan Chiang and Sandeep K. Gupta},
year = {2000},
doi = {10.1023/A:1008308430051},
url = {http://dx.doi.org/10.1023/A:1008308430051},
tags = {testing},
researchr = {https://researchr.org/publication/ChiangG00},
cites = {0},
citedby = {0},
journal = {J. Electronic Testing},
volume = {16},
number = {5},
pages = {427-442},
}