BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level

Chen-Huan Chiang, Sandeep K. Gupta. BIST TPG for Combinational Cluster (Glue Logic) Interconnect Testing at Board Level. In 7th Asian Test Symposium (ATS 98), 2-4 December 1998, Singapore. pages 244-252, IEEE Computer Society, 1998. [doi]

Authors

Chen-Huan Chiang

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Sandeep K. Gupta

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