The following publications are possibly variants of this publication:
- BIST TPG for Combinational Cluster Interconnect Testing at Board LevelChen-Huan Chiang, Sandeep K. Gupta. et, 16(5):427-442, 2000. [doi]
- BIST TPG for SRAM cluster interconnect testing at board levelChen-Huan Chiang, Sandeep K. Gupta. ats 2000: 58-65 [doi]
- BIST TPGs for Faults in Board Level Interconnect via Boundary ScanChen-Huan Chiang, Sandeep K. Gupta. vts 1997: 376-383 [doi]
- Efficient BIST TPG design and test set compaction via input reductionChih-Ang Chen, Sandeep K. Gupta. tcad, 17(8):692-705, 1998. [doi]
- LT-RTPG: a new test-per-scan BIST TPG for low switching activitySeongmoon Wang, Sandeep K. Gupta. tcad, 25(8):1565-1574, 2006. [doi]