A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology - researchr publication related

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A. Chowdhury, J. Ma, Y. Li, J. Guo, X. Zhang, P. B. Ramakrishna, J. Gu, Y. Wang, L. Liang, U. K. Shukla, K. Mohammad, H. Yan, Y. Sun, M. Lin, Z. Jiang, F. Khan, M. Yeoh, C. Su, J. Ding, M. Baecher, S. Parker, H. Wang, M. Seymour, Michael Wielgos, Ken Chang. A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology. In IEEE Symposium on VLSI Technology and Circuits 2024, Honolulu, HI, USA, June 16-20, 2024. pages 1-2, IEEE, 2024. [doi]

The following publications are possibly variants of this publication:

A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOSGautam R. Gangasani, A. Mostafa, A. Singh, Daniel W. Storaska, D. Prabakaran, K. Mohammad, Matthew Baecher, M. Shannon, Michael Sorna, Michael Wielgos, P. Jenkins, P. B. Ramakrishna, U. K. Shukla. vlsit 2024: 1-2 [doi]

10 Gb/s Duobinary transmitter with a 6-tap FFE using 180 nm CMOS technologyYinhang Zhang, Chao Yin, Xi Yang, Yongzheng Zhan. mj, 156:106530, 2025. [doi]

A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOSGautam Reddy Gangasani, D. Hanson, Daniel W. Storaska, H. H. Xu, M. Kelly, M. Shannon, Michael Sorna, Michael Wielgos, P. B. Ramakrishna, S. Shi, S. Parker, U. K. Shukla, W. Kelly, W. Su, Z. Yu. isscc 2022: 122-124 [doi]

11.1 A 1.7pJ/b 112Gb/s XSR Transceiver for Intra-Package Communication in 7nm FinFET TechnologyRamy Yousry, E.-Hung Chen, Yu-Ming Ying, Mohammed Abdullatif, Mohammad Elbadry, Ahmed ElShater, Tsz-Bin Liu, Joonyeong Lee, Dhinessh Ramachandran, Kaiz Wang, Chih-Hao Weng, Mau-Lin Wu, Tamer Ali. isscc 2021: 180-182 [doi]

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