Transistor and pin reordering for leakage reduction in CMOS circuits

Jae Woong Chun, C. Y. Roger Chen. Transistor and pin reordering for leakage reduction in CMOS circuits. Microelectronics Journal, 53:25-34, 2016. [doi]

@article{ChunC16-0,
  title = {Transistor and pin reordering for leakage reduction in CMOS circuits},
  author = {Jae Woong Chun and C. Y. Roger Chen},
  year = {2016},
  doi = {10.1016/j.mejo.2016.04.005},
  url = {http://dx.doi.org/10.1016/j.mejo.2016.04.005},
  researchr = {https://researchr.org/publication/ChunC16-0},
  cites = {0},
  citedby = {0},
  journal = {Microelectronics Journal},
  volume = {53},
  pages = {25-34},
}