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Jae Woong Chun, C. Y. Roger Chen. Transistor and pin reordering for leakage reduction in CMOS circuits. Microelectronics Journal, 53:25-34, 2016. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Performance Enhancement of CMOS VLSI Circuits by Transistor ReorderingBradley S. Carlson, C. Y. Roger Chen. dac 1993: 361-366 [doi] Leakage power reduction using the body bias and pin reordering techniqueJae Woong Chun, Chien-Yi Roger Chen. ieiceee, 13(3):20151052, 2016. [doi]
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