Yutaka Deguchi, Nagisa Ishiura, Shuzo Yajima. Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits. In DAC. pages 650-655, 1991. [doi]
@inproceedings{DeguchiIY91,
title = {Probabilistic CTSS: Analysis of Timing Error Probability in Asynchronous Logic Circuits},
author = {Yutaka Deguchi and Nagisa Ishiura and Shuzo Yajima},
year = {1991},
doi = {10.1145/127601.127745},
url = {http://doi.acm.org/10.1145/127601.127745},
tags = {analysis, logic},
researchr = {https://researchr.org/publication/DeguchiIY91},
cites = {0},
citedby = {0},
pages = {650-655},
booktitle = {DAC},
}