Post-layout timing simulation of CMOS circuits

Denis Deschacht, Michel Robert, Nadine Azémard-Crestani, Daniel Auvergne. Post-layout timing simulation of CMOS circuits. IEEE Trans. on CAD of Integrated Circuits and Systems, 12(8):1170-1177, 1993. [doi]

@article{DeschachtRAA93,
  title = {Post-layout timing simulation of CMOS circuits},
  author = {Denis Deschacht and Michel Robert and Nadine Azémard-Crestani and Daniel Auvergne},
  year = {1993},
  doi = {10.1109/43.238609},
  url = {http://doi.ieeecomputersociety.org/10.1109/43.238609},
  tags = {layout},
  researchr = {https://researchr.org/publication/DeschachtRAA93},
  cites = {0},
  citedby = {0},
  journal = {IEEE Trans. on CAD of Integrated Circuits and Systems},
  volume = {12},
  number = {8},
  pages = {1170-1177},
}