A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

Timothy O. Dickson, Yong Liu, Sergey V. Rylov, Ankur Agrawal, Seongwon Kim, Ping-Hsuan Hsieh, John F. Bulzacchelli, Mark A. Ferriss, Herschel A. Ainspan, Alexander Rylyakov, Benjamin D. Parker, Michael P. Beakes, Christian W. Baks, Lei Shan, Young Hoon Kwark, José A. Tierno, Daniel J. Friedman. A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology. J. Solid-State Circuits, 50(8):1917-1931, 2015. [doi]

@article{DicksonLRAKHBFA15,
  title = {A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology},
  author = {Timothy O. Dickson and Yong Liu and Sergey V. Rylov and Ankur Agrawal and Seongwon Kim and Ping-Hsuan Hsieh and John F. Bulzacchelli and Mark A. Ferriss and Herschel A. Ainspan and Alexander Rylyakov and Benjamin D. Parker and Michael P. Beakes and Christian W. Baks and Lei Shan and Young Hoon Kwark and José A. Tierno and Daniel J. Friedman},
  year = {2015},
  doi = {10.1109/JSSC.2015.2412688},
  url = {http://dx.doi.org/10.1109/JSSC.2015.2412688},
  researchr = {https://researchr.org/publication/DicksonLRAKHBFA15},
  cites = {0},
  citedby = {0},
  journal = {J. Solid-State Circuits},
  volume = {50},
  number = {8},
  pages = {1917-1931},
}