The effect of post-layout pin permutation on timing

Yuzheng Ding, Peter Suaris, Nan-Chi Chou. The effect of post-layout pin permutation on timing. In Herman Schmit, Steven J. E. Wilton, editors, Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005. pages 41-50, ACM, 2005. [doi]

@inproceedings{DingSC05,
  title = {The effect of post-layout pin permutation on timing},
  author = {Yuzheng Ding and Peter Suaris and Nan-Chi Chou},
  year = {2005},
  doi = {10.1145/1046192.1046199},
  url = {http://doi.acm.org/10.1145/1046192.1046199},
  tags = {layout},
  researchr = {https://researchr.org/publication/DingSC05},
  cites = {0},
  citedby = {0},
  pages = {41-50},
  booktitle = {Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005},
  editor = {Herman Schmit and Steven J. E. Wilton},
  publisher = {ACM},
  isbn = {1-59593-029-9},
}