Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators

Friedel Gerfers, Maurits Ortmanns, Yiannos Manoli. Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators. In ISCAS (4). pages 1076-1079, 2004. [doi]

@inproceedings{GerfersOM04,
  title = {Design issues and performance limitations of a clock jitter insensitive multibit DAC architecture for high-performance low-power CT Sigma Delta modulators},
  author = {Friedel Gerfers and Maurits Ortmanns and Yiannos Manoli},
  year = {2004},
  doi = {10.1109/ISCAS.2004.1328385},
  url = {http://dx.doi.org/10.1109/ISCAS.2004.1328385},
  tags = {architecture, design},
  researchr = {https://researchr.org/publication/GerfersOM04},
  cites = {0},
  citedby = {0},
  pages = {1076-1079},
  booktitle = {ISCAS (4)},
}