Robust Sequential Fault Testing of Iterative Logic Arrays - researchr publication related

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Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis. Robust Sequential Fault Testing of Iterative Logic Arrays. In 15th IEEE VLSI Test Symposium (VTS 97), April 27-May 1, 1997, Monterey, California, USA. pages 238-244, IEEE Computer Society, 1997. [doi]

The following publications are possibly variants of this publication:

Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic ArraysMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. TC, 49(10):1083-1099, 2000. [doi]

Testing combinational iterative logic arrays for realistic faultsDimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis. vts 1995: 35-41 [doi]

Testing CMOS combinational iterative logic arrays for realistic faultsDimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis. integration, 21(3):209-228, 1996. [doi]

Robustly Testable Array Multipliers under Realistic Sequential Cell Fault ModelMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian. vts 1998: 152-157 [doi]

Built-in sequential fault self-testing of array multipliersMihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis. tcad, 24(3):449-460, 2005. [doi]

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