The following publications are possibly variants of this publication:
- Using Dynamic Signal-Tracing to Debug Compiler-Optimized HLS Circuits on FPGAsJeffrey B. Goeders, Steven J. E. Wilton. fccm 2015: 127-134 [doi]
- Architecture Exploration for HLS-Oriented FPGA Debug OverlaysAl-Shahna Jamal, Jeffrey Goeders, Steven J. E. Wilton. fpga 2018: 209-218 [doi]
- Enabling Long Debug Traces of HLS Circuits Using Bandwidth-Limited Off-Chip Storage DevicesJeffrey Goeders. fccm 2017: 136-143 [doi]
- Adaptive Clock Management of HLS-generated Circuits on FPGAsKahlan Gibson, Esther Roorda, Daniel Holanda Noronha, Steven J. E. Wilton. trets, 15(4), 2022. [doi]
- Fast Turnaround HLS Debugging Using Dependency Analysis and Debug OverlaysAl-Shahna Jamal, Eli Cahill, Jeffrey Goeders, Steven J. E. Wilton. trets, 13(1), 2020. [doi]