The following publications are possibly variants of this publication:
- Stress-Aware Loops Mapping on CGRAs with Dynamic Multi-Map ReconfigurationJiangyuan Gu, Shouyi Yin, Leibo Liu, Shaojun Wei. tpds, 29(9):2105-2120, 2018. [doi]
- Battery-aware mapping optimization of loop nests for CGRAsYu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei. aspdac 2015: 767-772 [doi]
- Battery-Aware Loop Nests Mapping for CGRAsYu Peng, Shouyi Yin, Leibo Liu, Shaojun Wei. ieicet, 98-D(2):230-242, 2015. [doi]
- TAEM: Fast Transfer-Aware Effective Loop Mapping for Heterogeneous Resources on CGRAMingyang Kou, Jiangyuan Gu, Shaojun Wei, Hailong Yao, Shouyi Yin. dac 2020: 1-6 [doi]
- Stress-Aware Loops Mapping on CGRAs with Considering NBTI Aging EffectJiangyuan Gu, Shouyi Yin, Shaojun Wei. dac 2017: [doi]
- Trigger-Centric Loop Mapping on CGRAsShouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei. tvlsi, 24(5):1998-2002, 2016. [doi]
- Low-power loop pipelining mapping onto CGRA utilizing variable dual VDDBing Xu, Shouyi Yin, Leibo Liu, Shaojun Wei. mwscas 2014: 242-245 [doi]
- Mapping Multi-Level Loop Nests onto CGRAs Using Polyhedral OptimizationsDajiang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei. ieicet, 98-A(7):1419-1430, 2015. [doi]