Statistical Gate Sizing for Yield Enhancement at Post Layout Level - researchr publication authors

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Narender Hanchate, Nagarajan Ranganathan. Statistical Gate Sizing for Yield Enhancement at Post Layout Level. In 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil. pages 245-252, IEEE Computer Society, 2007. [doi]

This author has not been identified. Look up 'Narender Hanchate' in GoogleThis author has not been identified. Look up 'Nagarajan Ranganathan' in Google

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