Narender Hanchate, Nagarajan Ranganathan. Statistical Gate Sizing for Yield Enhancement at Post Layout Level. In 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil. pages 245-252, IEEE Computer Society, 2007. [doi]
@inproceedings{HanchateR07a,
title = {Statistical Gate Sizing for Yield Enhancement at Post Layout Level},
author = {Narender Hanchate and Nagarajan Ranganathan},
year = {2007},
doi = {10.1109/ISVLSI.2007.92},
url = {http://doi.ieeecomputersociety.org/10.1109/ISVLSI.2007.92},
tags = {layout},
researchr = {https://researchr.org/publication/HanchateR07a},
cites = {0},
citedby = {0},
pages = {245-252},
booktitle = {2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil},
publisher = {IEEE Computer Society},
}