Statistical Gate Sizing for Yield Enhancement at Post Layout Level - researchr publication related

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Narender Hanchate, Nagarajan Ranganathan. Statistical Gate Sizing for Yield Enhancement at Post Layout Level. In 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), May 9-11, 2007, Porto Alegre, Brazil. pages 245-252, IEEE Computer Society, 2007. [doi]

The following publications are possibly variants of this publication:

Integrated Gate and Wire Sizing at Post Layout LevelNarender Hanchate, Nagarajan Ranganathan. isvlsi 2007: 225-232 [doi]

Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise OptimizationNarender Hanchate, Nagarajan Ranganathan. isqed 2006: 92-97 [doi]

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