The following publications are possibly variants of this publication:
- A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS TechnologyAibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui 0004, Yong Zhou, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. glvlsi 2022: 255-260 [doi]
- Novel Low Cost and Double Node Upset Tolerant Latch Design for Nanoscale CMOS TechnologyAibin Yan, Zhengfeng Huang, Xiangsheng Fang, Xiaolin Xu, Huaguo Liang. ats 2016: 252-256 [doi]
- A Self-Recoverable, Frequency-Aware and Cost-Effective Robust Latch Design for Nanoscale CMOS TechnologyAibin Yan, Huaguo Liang, Zhengfeng Huang, Cuiyun Jiang, Maoxiang Yi. ieicet, 98-C(12):1171-1178, 2015. [doi]
- Novel Radiation-Hardened-by-Design (RHBD) 12T Memory Cell for Aerospace Applications in Nanoscale CMOS TechnologyJing Guo, Lei Zhu, Wenyi Liu, Hai Huang, Shanshan Liu, Tianqi Wang, Liyi Xiao, Zhigang Mao. tvlsi, 25(5):1593-1600, 2017. [doi]
- SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS processZhong-Li Tang, Chia-Wei Liang, Ming-Hsien Hsiao, Charles H.-P. Wen. dac 2022: 865-870 [doi]