Abstract is missing.
- Frontmatter [doi]
- QuantumNAT: quantum noise-aware training with noise injection, quantization and normalizationHanrui Wang 0002, Jiaqi Gu, Yongshan Ding 0001, Zirui Li, Frederic T. Chong, David Z. Pan, Song Han 0003. 1-6 [doi]
- Optimizing quantum circuit synthesis for permutations using recursionCynthia Chen, Bruno Schmitt, Helena Zhang, Lev S. Bishop, Ali Javadi-Abhar. 7-12 [doi]
- A fast and scalable qubit-mapping method for noisy intermediate-scale quantum computersSunghye Park, Daeyeon Kim, Minhyuk Kweon, Jae-Yoon Sim, Seokhyeong Kang. 13-18 [doi]
- Optimizing quantum circuit placement via machine learningHongxiang Fan, Ce Guo, Wayne Luk. 19-24 [doi]
- HERO: hessian-enhanced robust optimization for unifying and improving generalization and quantization performanceHuanrui Yang, Xiaoxuan Yang, Neil Zhenqiang Gong, Yiran Chen 0001. 25-30 [doi]
- Neural computation for robust and holographic face detectionMohsen Imani, Ali Zakeri, Hanning Chen, Taehyun Kim, Prathyush Poduval, Hyunsei Lee, Yeseong Kim, Elaheh Sadredini, Farhad Imani. 31-36 [doi]
- FHDnn: communication efficient and robust federated learning for AIoT networksRishikanth Chandrasekaran, Kazim Ergun, Jihyun Lee, Dhanush Nanjunda, Jaeyoung Kang 0001, Tajana Rosing. 37-42 [doi]
- ODHD: one-class brain-inspired hyperdimensional computing for outlier detectionRuixuan Wang, Xun Jiao, X. Sharon Hu. 43-48 [doi]
- High-level synthesis performance prediction using GNNs: benchmarking, modeling, and advancingNan Wu, Hang Yang, Yuan Xie, Pan Li, Cong Hao. 49-54 [doi]
- Automated accelerator optimization aided by graph neural networksAtefeh Sohrabizadeh, Yunsheng Bai, Yizhou Sun, Jason Cong. 55-60 [doi]
- Functionality matters in netlist representation learningZiyi Wang, Chen Bai, Zhuolun He, Guangliang Zhang, Qiang Xu, Tsung-Yi Ho, Bei Yu, Yu Huang. 61-66 [doi]
- EMS: efficient memory subsystem synthesis for spatial acceleratorsLiancheng Jia, Yuyue Wang, Jingwen Leng, Yun Liang 0001. 67-72 [doi]
- DA PUF: dual-state analog PUFJiliang Zhang 0002, Lin Ding, Zhuojun Chen, Wenshang Li, Gang Qu 0001. 73-78 [doi]
- PathFinder: side channel protection through automatic leaky paths identification and obfuscationHaocheng Ma, Qizhi Zhang, Ya Gao, Jiaji He, Yiqiang Zhao, Yier Jin. 79-84 [doi]
- LOCK&ROLL: deep-learning power side-channel attack mitigation using emerging reconfigurable devices and logic lockingGaurav Kolhe, Tyler David Sheaves, Kevin Immanuel Gubbi, Soheil Salehi, Setareh Rafatirad, Sai Manoj P. D., Avesta Sasan, Houman Homayoun. 85-90 [doi]
- Efficient access scheme for multi-bank based NTT architecture through conflict graphXiangren Chen, Bohan Yang 0004, Yong Lu, Shouyi Yin, Shaojun Wei, Leibo Liu. 91-96 [doi]
- InfoX: an energy-efficient ReRAM accelerator design with information-lossless low-bit ADCsYintao He, Songyun Qu, Ying Wang 0001, Bing Li 0017, Huawei Li, Xiaowei Li 0001. 97-102 [doi]
- PHANES: ReRAM-based photonic accelerator for deep neural networksYinyi Liu, Jiaqi Liu, Yuxiang Fu, Shixi Chen, Jiaxu Zhang, Jiang Xu 0001. 103-108 [doi]
- CP-SRAM: charge-pulsation SRAM marco for ultra-high energy-efficiency computing-in-memoryHe Zhang, Linjun Jiang, Jianxin Wu, Tingran Chen, Junzhan Liu, Wang Kang, Weisheng Zhao. 109-114 [doi]
- CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network accelerationLiukai Xu, Songyuan Liu, Zhi Li, Dengfeng Wang, Yiming Chen, Yanan Sun 0003, Xueqing Li, Weifeng He, Shi Xu. 115-120 [doi]
- Chiplet actuary: a quantitative cost model and multi-chiplet architecture explorationYinxiao Feng, Kaisheng Ma. 121-126 [doi]
- PANORAMA: divide-and-conquer approach for mapping complex loop kernels on CGRADhananjaya Wijerathne, Zhaoying Li, Thilini Kaushalya Bandara, Tulika Mitra. 127-132 [doi]
- A fast parameter tuning framework via transfer learning and multi-objective bayesian optimizationZheng Zhang, Tinghuan Chen, Jiaxin Huang, Meng Zhang. 133-138 [doi]
- PriMax: maximizing DSL application performance with selective primitive accelerationNicholas Wendt, Todd M. Austin, Valeria Bertacco. 139-144 [doi]
- Accelerating and pruning CNNs for semantic segmentation on FPGAPierpaolo Morì, Manoj Rohit Vemparala, Nael Fasfous, Saptarshi Mitra, Sreetama Sarkar, Alexander Frickenstein, Lukas Frickenstein, Domenik Helms, Naveen Shankar Nagaraja, Walter Stechele, Claudio Passerone. 145-150 [doi]
- SoftSNN: low-cost fault tolerance for spiking neural network accelerators under soft errorsRachmad Vidya Wicaksana Putra, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 151-156 [doi]
- A joint management middleware to improve training performance of deep recommendation systems with SSDsChun-Feng Wu, Carole-Jean Wu, Gu-Yeon Wei, David Brooks 0001. 157-162 [doi]
- The larger the fairer?: small neural networks can achieve fairness for edge devicesYi-sheng, Junhuan Yang, Yawen Wu, Kevin Mao, Yiyu Shi, Jingtong Hu, Weiwen Jiang, Lei Yang. 163-168 [doi]
- SCAIE-V: an open-source SCAlable interface for ISA extensions for RISC-V processorsMihaela Damian, Julian Oppermann, Christoph Spang 0001, Andreas Koch 0001. 169-174 [doi]
- A scalable symbolic simulation tool for low power embedded systemsSubhash Sethumurugan, Shashank Hegde, Hari Cherupalli, John Sartori. 175-180 [doi]
- Designing critical systems with iterative automated safety analysisRan Wei, Zhe Jiang 0004, Xiaoran Guo, HaiTao Mei, Athanasios Zolotas, Tim Kelly. 181-186 [doi]
- Efficient ensembles of graph neural networksAmrit Nagarajan, Jacob R. Stevens, Anand Raghunathan. 187-192 [doi]
- Sign bit is enough: a learning synchronization framework for multi-hop all-reduce with ultimate compressionFeijie Wu, Shiqi He, Song Guo 0001, Zhihao Qu, Haozhao Wang, Weihua Zhuang, Jie Zhang 0076. 193-198 [doi]
- GLite: a fast and efficient automatic graph-level optimizer for large-scale DNNsJiaqi Li 0006, Min Peng, Qingan Li, Meizheng Peng, Mengting Yuan. 199-204 [doi]
- Contrastive quant: quantization makes stronger contrastive learningYonggan Fu, Qixuan Yu, Meng Li, Xu Ouyang, Vikas Chandra, Yingyan Lin. 205-210 [doi]
- Serpens: a high bandwidth memory based accelerator for general-purpose sparse matrix-vector multiplicationLinghao Song, Yuze Chi, Licheng Guo, Jason Cong. 211-216 [doi]
- An energy-efficient seizure detection processor using event-driven multi-stage CNN classification and segmented data processing with adaptive channel selectionJiahao Liu, Zirui Zhong, Yong Zhou, Hui Qiu, Jianbiao Xiao, Jiajing Fan, Zhaomin Zhang, Sixu Li, Yiming Xu, Siqi Yang 0002, Weiwei Shan, Shuisheng Lin, Liang Chang 0002, Jun Zhou 0017. 217-222 [doi]
- PatterNet: explore and exploit filter patterns for efficient deep neural networksBehnam Khaleghi, Uday Mallappa, Duygu Yaldiz, Haichao Yang, Monil Shah, Jaeyoung Kang 0001, Tajana Rosing. 223-228 [doi]
- 2SR: an end-to-end video CODEC assisted system for super resolution accelerationZhuoran Song, Zhongkai Yu, Naifeng Jing, Xiaoyao Liang. 229-234 [doi]
- MATCHA: a fast and energy-efficient accelerator for fully homomorphic encryption over the torusLei Jiang 0001, Qian Lou, Nrushad Joshi. 235-240 [doi]
- VirTEE: a full backward-compatible TEE with native live migration and secure I/OJianqiang Wang, Pouya Mahmoody, Ferdinand Brasser, Patrick Jauernig, Ahmad-Reza Sadeghi, Donghui Yu, Dahan Pan, Yuanyuan Zhang 0002. 241-246 [doi]
- Apple vs. EMA: electromagnetic side channel attacks on apple CoreCryptoGregor Haas, Aydin Aysu. 247-252 [doi]
- Algorithm/architecture co-design for energy-efficient acceleration of multi-task DNNJaekang Shin, Seungkyu Choi, Jongwoo Ra, Lee-Sup Kim. 253-258 [doi]
- EBSP: evolving bit sparsity patterns for hardware-friendly inference of quantized deep neural networksFangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Zhezhi He, Naifeng Jing, Xiaoyao Liang, Li Jiang. 259-264 [doi]
- A time-to-first-spike coding and conversion aware training for energy-efficient deep spiking neural network processor designDongwoo Lew, Kyungchul Lee, Jongsun Park 0001. 265-270 [doi]
- XMA: a crossbar-aware multi-task adaption framework via shift-based mask learning methodFan Zhang, Li Yang, Jian Meng, Jae-sun Seo, Yu Kevin Cao, Deliang Fan. 271-276 [doi]
- SWIM: selective write-verify for computing-in-memory neural acceleratorsZheyu Yan, Xiaobo Sharon Hu, Yiyu Shi. 277-282 [doi]
- Enabling efficient deep convolutional neural network-based sensor fusion for autonomous drivingXiaoming Zeng, Zhendong Wang, Yang Hu 0001. 283-288 [doi]
- Zhuyi: perception processing rate estimation for safety in autonomous vehiclesYu-Shun Hsiao, Siva Kumar Sastry Hari, Michal Filipiuk, Timothy Tsai 0002, Michael B. Sullivan 0001, Vijay Janapa Reddi, Vasu Singh, Stephen W. Keckler. 289-294 [doi]
- Processing-in-SRAM acceleration for ultra-low power visual 3D perceptionYuquan He, Songyun Qu, Gangliang Lin, Cheng Liu, Lei Zhang 0008, Ying Wang. 295-300 [doi]
- Response time analysis for dynamic priority scheduling in ROS2Abdullah Al Arafat, Sudharsan Vaidhun, Kurt M. Wilson, Jinghao Sun, Zhishan Guo. 301-306 [doi]
- Voltage prediction of drone battery reflecting internal temperatureJiwon Kim, Seunghyeok Jeon, Jaehyun Kim, Hojung Cha. 307-312 [doi]
- A near-storage framework for boosted data preprocessing of mass spectrum clusteringWeihong Xu, Jaeyoung Kang 0001, Tajana Rosing. 313-318 [doi]
- MetaZip: a high-throughput and efficient accelerator for DEFLATERuihao Gao, Xueqi Li, Yewen Li, Xun Wang, Guangming Tan. 319-324 [doi]
- Enabling fast uncertainty estimation: accelerating bayesian transformers via algorithmic and hardware optimizationsHongxiang Fan, Martin Ferianc, Wayne Luk. 325-330 [doi]
- Eventor: an efficient event-based monocular multi-view stereo accelerator on FPGA platformMingjun Li, Jianlei Yang 0001, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao. 331-336 [doi]
- GEML: GNN-based efficient mapping method for large loop applications on CGRAMingyang Kou, Jun Zeng, Boxiao Han, Fei Xu, Jiangyuan Gu, Hailong Yao. 337-342 [doi]
- Mixed-granularity parallel coarse-grained reconfigurable architectureJinyi Deng, Linyun Zhang, Lei Wang, Jiawei Liu, Kexiang Deng, Shibin Tang, Jiangyuan Gu, Boxiao Han, Fei Xu, Leibo Liu, Shaojun Wei, Shouyi Yin. 343-348 [doi]
- GuardNN: secure accelerator architecture for privacy-preserving deep learningWeizhe Hua, Muhammad Umar, Zhiru Zhang, G. Edward Suh. 349-354 [doi]
- SRA: a secure ReRAM-based DNN acceleratorLei Zhao, Youtao Zhang, Jun Yang. 355-360 [doi]
- 2: secure two-party arbitrary-bitwidth quantized neural network predictionsLiyan Shen, Ye Dong, Binxing Fang, Jinqiao Shi, Xuebin Wang, Shengli Pan 0003, Ruisheng Shi. 361-366 [doi]
- Adaptive neural recovery for highly robust brain-like representationPrathyush Poduval, Yang Ni, Yeseong Kim, Kai Ni 0004, Raghavan Kumar, Rosario Cammarota, Mohsen Imani. 367-372 [doi]
- Efficiency attacks on spiking neural networksSarada Krithivasan, Sanchari Sen, Nitin Rathi, Kaushik Roy 0001, Anand Raghunathan. 373-378 [doi]
- L-QoCo: learning to optimize cache capacity overloading in storage systemsJi Zhang, Xijun Li, Xiyao Zhou, Mingxuan Yuan, Zhuo Cheng, Keji Huang, Yifan Li. 379-384 [doi]
- Pipette: efficient fine-grained reads for SSDsShuhan Bai, Hu Wan 0001, Yun Huang, Xuan Sun 0003, Fei Wu 0005, Changsheng Xie, Hung-Chih Hsieh, Tei-Wei Kuo, Chun Jason Xue. 385-390 [doi]
- CDB: critical data backup design for consumer devices with high-density flash based hybrid storageLongfei Luo, Dingcui Yu, Liang Shi, Chuanming Ding, Changlong Li, Edwin H.-M. Sha. 391-396 [doi]
- SS-LRU: a smart segmented LRU cachingChunhua Li, Man Wu, Yuhan Liu, Ke Zhou 0001, Ji Zhang, Yunqing Sun. 397-402 [doi]
- NobLSM: an LSM-tree with non-blocking writes for SSDsHaoran Dang, Chongnan Ye, Yanpeng Hu, Chundong Wang 0001. 403-408 [doi]
- TailCut: improving performance and lifetime of SSDs using pattern-aware state encodingJaeyong Lee, Myungsuk Kim, Wonil Choi, Sanggu Lee, Jihong Kim 0001. 409-414 [doi]
- HIMap: a heuristic and iterative logic synthesis approachXing Li, Lei Chen 0031, Fan Yang, Mingxuan Yuan, Hongli Yan, Yupeng Wan. 415-420 [doi]
- Improving LUT-based optimization for ASICsWalter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon. 421-426 [doi]
- NovelRewrite: node-level parallel AIG rewritingShiju Lin, Jinwei Liu, Tianji Liu, Martin D. F. Wong, Evangeline F. Y. Young. 427-432 [doi]
- Search space characterization for approximate logic synthesisLinus Witschen, Tobias Wiersema, Lucas Reuter, Marco Platzner. 433-438 [doi]
- SEALS: sensitivity-driven efficient approximate logic synthesisChang Meng, Xuan Wang, Jiajun Sun, Sijun Tao, Wei Wu, Zhihang Wu, Leibin Ni, Xiaolong Shen, Junfeng Zhao, Weikang Qian. 439-444 [doi]
- Beyond local optimality of buffer and splitter insertion for AQFP circuitsSiang-Yun Lee, Heinz Riener, Giovanni De Micheli. 445-450 [doi]
- NAX: neural architecture and memristive xbar based accelerator co-designShubham Negi, Indranil Chakraborty, Aayush Ankit, Kaushik Roy 0001. 451-456 [doi]
- MC-CIM: a reconfigurable computation-in-memory for efficient stereo matching cost computationZhiheng Yue, Yabing Wang, Leibo Liu, Shaojun Wei, Shouyi Yin. 457-462 [doi]
- iMARS: an in-memory-computing architecture for recommendation systemsMengyuan Li, Ann Franchesca Laguna, Dayane Reis, Xunzhao Yin, Michael T. Niemier, X. Sharon Hu. 463-468 [doi]
- ReGNN: a ReRAM-based heterogeneous architecture for general graph neural networksCong Liu, Haikun Liu, Hai Jin 0001, Xiaofei Liao, Yu Zhang, Zhuohui Duan, Jiahong Xu, Huize Li. 469-474 [doi]
- You only search once: on lightweight differentiable architecture search for resource-constrained embedded platformsXiangzhong Luo, Di Liu, Hao Kong, Shuo Huai, Hui Chen, Weichen Liu. 475-480 [doi]
- EcoFusion: energy-aware adaptive sensor fusion for efficient autonomous vehicle perceptionArnav Vaibhav Malawade, Trier Mortlock, Mohammad Abdullah Al Faruque. 481-486 [doi]
- Human emotion based real-time memory and computation management on resource-limited edge devicesYijie Wei, Zhiwei Zhong, Jie Gu 0001. 487-492 [doi]
- Hierarchical memory-constrained operator scheduling of neural architecture search networksZihan Wang, Chengcheng Wan, Yuting Chen, Ziyi Lin, He Jiang 0001, Lei Qiao. 493-498 [doi]
- MIME: adapting a single neural network for multi-task inference with memory-efficient dynamic pruningAbhiroop Bhattacharjee, Yeshwanth Venkatesha, Abhishek Moitra, Priyadarshini Panda. 499-504 [doi]
- Sniper: cloud-edge collaborative inference scheduling with neural network similarity modelingWeihong Liu, Jiawei Geng, Zongwei Zhu, Jing Cao, Zirui Lian. 505-510 [doi]
- LPCA: learned MRC profiling based cache allocation for file storage systemsYibin Gu, Yifan Li, Hua Wang, Li Liu, Ke Zhou, Wei Fang, Gang Hu, Jinhu Liu, Zhuo Cheng. 511-516 [doi]
- Equivalence checking paradigms in quantum circuit design: a case studyTom Peham, Lukas Burgholzer, Robert Wille. 517-522 [doi]
- Accurate BDD-based unitary operator manipulation for scalable and robust quantum circuit verificationChun-Yu Wei, Yuan-Hung Tsai, Chiao-Shan Jhang, Jie-Hong R. Jiang. 523-528 [doi]
- Handling non-unitaries in quantum circuit equivalence checkingLukas Burgholzer, Robert Wille. 529-534 [doi]
- A bridge-based algorithm for simultaneous primal and dual defects compression on topologically quantum-error-corrected circuitsWei-Hsiang Tseng, Yao-Wen Chang. 535-540 [doi]
- FaSe: fast selective flushing to mitigate contention-based cache timing attacksTuo Li 0001, Sri Parameswaran. 541-546 [doi]
- Conditional address propagation: an efficient defense mechanism against transient execution attacksPeinan Li, Rui Hou 0001, Lutan Zhao, Yifan Zhu, Dan Meng. 547-552 [doi]
- Timed speculative attacks exploiting store-to-load forwarding bypassing cache-based countermeasuresAnirban Chakraborty, Nikhilesh Singh, Sarani Bhattacharya, Chester Rebeiro, Debdeep Mukhopadhyay. 553-558 [doi]
- DARPT: defense against remote physical attack based on TDC in multi-tenant scenarioFan Zhang 0010, Zhiyong Wang, Haoting Shen, Bolin Yang, Qianmei Wu, Kui Ren 0001. 559-564 [doi]
- GNNIE: GNN inference engine with load-balancing and graph-specific cachingSudipta Mondal, Susmita Dey Manasi, Kishor Kunal, Ramprasath S, Sachin S. Sapatnekar. 565-570 [doi]
- SALO: an efficient spatial accelerator enabling hybrid sparse attention mechanisms for long sequencesGuan Shen, Jieru Zhao, Quan Chen, Jingwen Leng, Chao Li, Minyi Guo. 571-576 [doi]
- NN-LUT: neural approximation of non-linear operations for efficient transformer inferenceJoonsang Yu, Junki Park, Seongmin Park, Minsoo Kim, Sihwa Lee, Dong-hyun Lee, Jungwook Choi. 577-582 [doi]
- Self adaptive reconfigurable arrays (SARA): learning flexible GEMM accelerator configuration and mapping-space using MLAnanda Samajdar, Eric Qin 0001, Michael Pellauer, Tushar Krishna. 583-588 [doi]
- Enabling hard constraints in differentiable neural network and accelerator co-explorationDeokki Hong, Kanghyun Choi, Hyeyoon Lee, Joonsang Yu, Noseong Park, Youngsok Kim, Jinho Lee. 589-594 [doi]
- Heuristic adaptability to input dynamics for SpMM on CPUsGuohao Dai, Guyue Huang, Shang Yang, Zhongming Yu, Hengrui Zhang, Yufei Ding, Yuan Xie, Huazhong Yang, Yu Wang 0002. 595-600 [doi]
- H2H: heterogeneous model to heterogeneous system mapping with computation and communication awarenessXinyi Zhang, Cong Hao, Peipei Zhou 0001, Alex Jones, Jingtong Hu. 601-606 [doi]
- PARIS and ELSA: an elastic scheduling algorithm for reconfigurable multi-GPU inference serversYunseong Kim, Yujeong Choi, Minsoo Rhu. 607-612 [doi]
- Pursuing more effective graph spectral sparsifiers via approximate trace reductionZhiqiang Liu, Wenjian Yu. 613-618 [doi]
- Accelerating nonlinear DC circuit simulation with reinforcement learningZhou Jin 0001, Haojie Pei, Yichao Dong, Xiang Jin, Xiao Wu, Wei W. Xing, Dan Niu. 619-624 [doi]
- An efficient yield optimization method for analog circuits via gaussian process classification and varying-sigma samplingXiaodong Wang, Changhao Yan, Fan Yang, Dian Zhou, Xuan Zeng 0001. 625-630 [doi]
- Partition and place finite element model on wafer-scale engineJinwei Liu, Xiaopeng Zhang 0007, Shiju Lin, Xinshi Zang, Jingsong Chen, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young. 631-636 [doi]
- CNN-inspired analytical global placement for large-scale heterogeneous FPGAsHuimin Wang, Xingyu Tong, Chenyue Ma, Runming Shi, Jianli Chen, Kun Wang, Jun Yu, Yao-Wen Chang. 637-642 [doi]
- High-performance placement for large-scale heterogeneous FPGAs with clock constraintsZiran Zhu, Yangjie Mei, Zijun Li, Jingwen Lin, Jianli Chen, Jun Yang, Yao-Wen Chang. 643-648 [doi]
- Multi-electrostatic FPGA placement considering SLICEL-SLICEM heterogeneity and clock feasibilityJing Mai, Yibai Meng, Zhixiong Di, Yibo Lin. 649-654 [doi]
- QOC: quantum on-chip training with parameter shift and gradient pruningHanrui Wang 0002, Zirui Li, Jiaqi Gu, Yongshan Ding 0001, David Z. Pan, Song Han 0003. 655-660 [doi]
- Memory-efficient training of binarized neural networks on the edgeMikail Yayla, Jian-Jia Chen. 661-666 [doi]
- DeepGate: learning neural representations of logic gatesMin Li 0019, Sadaf Khan, Zhengyuan Shi, Naixing Wang, Huang Yu, Qiang Xu 0001. 667-672 [doi]
- Bipolar vector classifier for fault-tolerant deep neural networksSuyong Lee, Insu Choi, Joon-Sung Yang. 673-678 [doi]
- HDLock: exploiting privileged encoding to protect hyperdimensional computing models against IP stealingShijin Duan, Shaolei Ren, Xiaolin Xu. 679-684 [doi]
- Terminator on SkyNet: a practical DVFS attack on DNN hardware IP for UAV object detectionJunge Xu, Bohan Xuan, Anlin Liu, Mo Sun, Fan Zhang 0010, Zeke Wang, Kui Ren 0001. 685-690 [doi]
- AL-PA: cross-device profiled side-channel attack using adversarial learningPei Cao, Hongyi Zhang, Dawu Gu, Yan Lu, Yidong Yuan. 691-696 [doi]
- DETERRENT: detecting trojans using reinforcement learningVasudev Gohil, Satwik Patnaik, Hao Guo, Dileep Kalathil, Jeyavijayan (JV) Rajendran. 697-702 [doi]
- Exploiting data locality in memory for ORAM to reduce memory access overheadsJinxi Kuang, Minghua Shen, Yutong Lu, Nong Xiao. 703-708 [doi]
- HWST128: complete memory safety accelerator on RISC-V with metadata compressionHsu-Kang Dow, Tuo Li 0001, Sri Parameswaran. 709-714 [doi]
- RegVault: hardware assisted selective data randomization for operating system kernelsJinyan Xu, Haoran Lin, Ziqi Yuan, Wenbo Shen, Yajin Zhou, Rui Chang, Lei Wu 0012, Kui Ren 0001. 715-720 [doi]
- ASAP: reconciling asynchronous real-time operations and proofs of execution in simple embedded systemsAdam Caulfield, Norrathep Rattanavipanon, Ivan De Oliveira Nunes. 721-726 [doi]
- Towards a formally verified hardware root-of-trust for data-oblivious computingLucas Deutschmann, Johannes Müller, Mohammad Rahmani Fadiheh, Dominik Stoffel, Wolfgang Kunz. 727-732 [doi]
- A scalable SIMD RISC-V based processor with customized vector extensions for CRYSTALS-kyberHuimin Li, Nele Mentens, Stjepan Picek. 733-738 [doi]
- Hexagons are the bestagons: design automation for silicon dangling bond logicMarcel Walter, Samuel Sze Hang Ng, Konrad Walus, Robert Wille. 739-744 [doi]
- Improving compute in-memory ECC reliability with successive correctionBrian Crafton, Zishen Wan, Samuel Spetalnick, Jong-Hyeok Yoon, Wei Wu, Carlos Tokunaga, Vivek De, Arijit Raychowdhury. 745-750 [doi]
- Energy efficient data search design and optimization based on a compact ferroelectric FET content addressable memoryJiahao Cai, Mohsen Imani, Kai Ni 0004, Grace Li Zhang, Bing Li 0005, Ulf Schlichtmann, Cheng Zhuo, Xunzhao Yin. 751-756 [doi]
- CamSkyGate: camouflaged skyrmion gates for protecting ICsYuqiao Zhang, Chunli Tang, Peng Li, Ujjwal Guin. 757-762 [doi]
- GNN-based concentration prediction for random microfluidic mixersWeiqing Ji, Xingzhuo Guo, Shouan Pan, Tsung-Yi Ho, Ulf Schlichtmann, Hailong Yao. 763-768 [doi]
- Designing ML-resilient locking at register-transfer levelDominik Sisejkovic, Luca Collini, Benjamin Tan 0001, Christian Pilato, Ramesh Karri, Rainer Leupers. 769-774 [doi]
- O'clock: lock the clock via clock-gating for SoC IP protectionM. Sazadur Rahman, Rui Guo, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mohamed Abdel-moneum, Mark M. Tehranipoor. 775-780 [doi]
- ALICE: an automatic design flow for eFPGA redactionChiara Muscari Tomajoli, Luca Collini, Jitendra Bhandari, Abdul Khader Thalakkattu Moosa, Benjamin Tan 0001, Xifan Tang, Pierre-Emmanuel Gaillardon, Ramesh Karri, Christian Pilato. 781-786 [doi]
- DELTA: DEsigning a stealthy trigger mechanism for analog hardware trojans and its detection analysisNishant Gupta, Mohil Sandip Desai, Mark Wijtvliet, Shubham Rai, Akash Kumar 0001. 787-792 [doi]
- VIPR-PCB: a machine learning based golden-free PCB assurance frameworkAritra Bhattacharyay, Prabuddha Chakraborty, Jonathan Cruz, Swarup Bhunia. 793-798 [doi]
- CLIMBER: defending phase change memory against inconsistent write attacksZhuohui Duan, Haobo Wang, Haikun Liu, Xiaofei Liao, Hai Jin 0001, Yu Zhang, Fubing Mao. 799-804 [doi]
- Rethinking key-value store for byte-addressable optane persistent memorySung-Ming Wu, Li-Pin Chang. 805-810 [doi]
- libcrpm: improving the checkpoint performance of NVMFeng Ren, Kang Chen, Yongwei Wu. 811-816 [doi]
- Scalable crash consistency for secure persistent memoryMing Zhang, Yu Hua 0001, Xuan Li, Hao Xu. 817-822 [doi]
- Don't open row: rethinking row buffer policy for improving performance of non-volatile memoriesYongho Lee, Osang Kwon, Seokin Hong. 823-828 [doi]
- SMART: on simultaneously marching racetracks to improve the performance of racetrack-based main memoryXiangjun Peng, Ming-Chang Yang, Ho Ming Tsui, Chi Ngai Leung, Wang Kang. 829-834 [doi]
- SAPredictor: a simple and accurate self-adaptive predictor for hierarchical hybrid memory systemYujuan Tan, Wei Chen, Zhulin Ma, Dan Xiao, Zhichao Yan, Duo Liu, Xianzhang Chen. 835-840 [doi]
- AVATAR: an aging- and variation-aware dynamic timing analyzer for application-based DVAFSZuodong Zhang, Zizheng Guo, Yibo Lin, Runsheng Wang, Ru Huang. 841-846 [doi]
- A defect tolerance framework for improving yieldShiva Shankar Thiagarajan, Suriyaprakash Natarajan, Yiorgos Makris. 847-852 [doi]
- Winograd convolution: a perspective from fault toleranceXinghua Xue, Haitong Huang, Cheng Liu, Tao Luo, Lei Zhang, Ying Wang. 853-858 [doi]
- Towards resilient analog in-memory deep learning via data layout re-organizationMuhammad Rashedul Haq Rashed, Amro Awad, Sumit Kumar Jha 0001, Rickard Ewetz. 859-864 [doi]
- SEM-latch: a lost-cost and high-performance latch design for mitigating soft errors in nanoscale CMOS processZhong-Li Tang, Chia-Wei Liang, Ming-Hsien Hsiao, Charles H.-P. Wen. 865-870 [doi]
- BlueSeer: AI-driven environment detection via BLE scansValentin Poirot, Oliver Harms, Hendric Martens, Olaf Landsiedel. 871-876 [doi]
- Compressive sensing based asymmetric semantic image compression for resource-constrained IoT systemYujun Huang, Bin Chen, Jianghui Zhang, Qiu Han, Shu-Tao Xia. 877-882 [doi]
- R2B: high-efficiency and fair I/O scheduling for multi-tenant with differentiated demandsDiansen Sun, Yunpeng Chai, Chaoyang Liu, Weihao Sun, Qingpeng Zhang. 883-888 [doi]
- Fast and scalable human pose estimation using mmWave point cloudSizhe An, Ümit Y. Ogras. 889-894 [doi]
- VWR2A: a very-wide-register reconfigurable-array architecture for low-power embedded devicesBenoît W. Denkinger, Miguel Peón Quirós, Mario Konijnenburg, David Atienza, Francky Catthoor. 895-900 [doi]
- Alleviating datapath conflicts and design centralization in graph analytics accelerationHaiyang Lin, Mingyu Yan, Duo Wang, Mo Zou, Fengbin Tu, Xiaochun Ye, Dongrui Fan, Yuan Xie 0001. 901-906 [doi]
- Hyperdimensional hashing: a robust and efficient dynamic hash tableMike Heddes, Igor Nunes, Tony Givargis, Alexandru Nicolau, Alexander V. Veidenbaum. 907-912 [doi]
- In-situ self-powered intelligent vision system with inference-adaptive energy scheduling for BNN-based always-on perceptionMaimaiti Nazhamaiti, Haijin Su, Han Xu, Zheyu Liu, Fei Qiao, Qi Wei 0001, Zidong Du, Xinghua Yang, Li Luo. 913-918 [doi]
- Adaptive window-based sensor attack detection for cyber-physical systemsLin Zhang, Zifan Wang, Mengyu Liu, Fanxin Kong. 919-924 [doi]
- Design-while-verify: correct-by-construction control learning with verification in the loopYixuan Wang, Chao Huang 0015, Zhaoran Wang, Zhilu Wang, Qi Zhu 0002. 925-930 [doi]
- GaBAN: a generic and flexibly programmable vector neuro-processor on FPGAJiajie Chen, Le Yang, Youhui Zhang. 931-936 [doi]
- ADEPT: automatic differentiable DEsign of photonic tensor coresJiaqi Gu, Hanqing Zhu, Chenghao Feng, Zixuan Jiang, Mingjie Liu, Shuhan Zhang, Ray T. Chen, David Z. Pan. 937-942 [doi]
- Unicorn: a multicore neuromorphic processor with flexible fan-in and unconstrained fan-out for neuronsZhijie Yang, Lei Wang, Yao Wang, LingHui Peng, Xiaofan Chen, Xun Xiao, Yaohua Wang, Weixia Xu. 943-948 [doi]
- Effective zero compression on ReRAM-based sparse DNN acceleratorsHoon Shin, Rihae Park, Seung Yul Lee, Yeonhong Park, Hyunseung Lee, Jae W. Lee. 949-954 [doi]
- Y-architecture-based flip-chip routing with dynamic programming-based bend minimizationSzu-Ru Nie, Yen-Ting Chen, Yao-Wen Chang. 955-960 [doi]
- Towards collaborative intelligence: routability estimation based on decentralized private dataJingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li 0005, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen 0001. 961-966 [doi]
- A2-ILT: GPU accelerated ILT with spatial attention mechanismQijing Wang, Bentian Jiang, Martin D. F. Wong, Evangeline F. Y. Young. 967-972 [doi]
- Generic lithography modeling with dual-band optics-inspired neural networksHaoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar, Brucek Khailany, Vivek Singh, Haoxing Ren. 973-978 [doi]
- Statistical computing framework and demonstration for in-memory computing systemsBonan Zhang, Peter Deaville, Naveen Verma. 979-984 [doi]
- Write or not: programming scheme optimization for RRAM-based neuromorphic computingZiqi Meng, Yanan Sun 0003, Weikang Qian. 985-990 [doi]
- ReSMA: accelerating approximate string matching using ReRAM-based content addressable memoryHuize Li, Hai Jin 0001, Long Zheng 0003, Yu Huang 0013, Xiaofei Liao, Zhuohui Duan, Dan Chen, Chuangyi Gui. 991-996 [doi]
- VStore: in-storage graph based vector search acceleratorShengwen Liang, Ying Wang, Ziming Yuan, Cheng Liu, Huawei Li, Xiaowei Li. 997-1002 [doi]
- Scaled-CBSC: scaled counting-based stochastic computing multiplication for improved accuracyShuyuan Yu, Sheldon X.-D. Tan. 1003-1008 [doi]
- Tailor: removing redundant operations in memristive analog neural network acceleratorsXingchen Li, Zhihang Yuan, Guangyu Sun 0003, Liang Zhao, Zhichao Lu. 1009-1014 [doi]
- Domain knowledge-infused deep learning for automated analog/radio-frequency circuit parameter optimizationWeidong Cao, Mouhacine Benosman, Xuan Zhang, Rui Ma. 1015-1020 [doi]
- A cost-efficient fully synthesizable stochastic time-to-digital converter design based on integral nonlinearity scramblingQiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen. 1021-1026 [doi]
- Using machine learning to optimize graph execution on NUMA machinesHiago Mayk G. de A. Rocha, Janaina Schwarzrock, Arthur Francisco Lorenzon, Antonio Carlos Schneider Beck. 1027-1032 [doi]
- HCG: optimizing embedded code generation of simulink with SIMD instruction synthesisZhuo Su 0005, Zehong Yu, Dongyan Wang, Yixiao Yang, Yu Jiang, Rui Wang, Wanli Chang 0001, Jiaguang Sun. 1033-1038 [doi]
- Raven: a novel kernel debugging tool on RISC-VHongyi Lu, Fengwei Zhang. 1039-1044 [doi]
- GTuner: tuning DNN computations on GPU via graph attention networkQi Sun, Xinyun Zhang, Hao Geng, Yuxuan Zhao, Yang Bai, Haisheng Zheng, Bei Yu 0001. 1045-1050 [doi]
- Pref-X: a framework to reveal data prefetching in commercial in-order coresQuentin Huppert, Francky Catthoor, Lionel Torres, David Novo. 1051-1056 [doi]
- Architecting DDR5 DRAM caches for non-volatile memory systemsXin Xin, Wanyi Zhu, Li Zhao. 1057-1062 [doi]
- GraphRing: an HMC-ring based graph processing framework with optimized data movementZerun Li, Xiaoming Chen, Yinhe Han. 1063-1068 [doi]
- AxoNN: energy-aware execution of neural network inference on multi-accelerator heterogeneous SoCsIsmet Dagli, Alexander Cieslewicz, Jedidiah McClurg, Mehmet E. Belviranli. 1069-1074 [doi]
- PIPF-DRAM: processing in precharge-free DRAMNezam Rohbani, Mohammad Arman Soleimani, Hamid Sarbazi-Azad. 1075-1080 [doi]
- TAIM: ternary activation in-memory computing hardware with 6T SRAM arrayNameun Kang, HyungJun Kim, Hyunmyung Oh, Jae-Joon Kim. 1081-1086 [doi]
- PIM-DH: ReRAM-based processing-in-memory architecture for deep hashing accelerationFangxin Liu, Wenbo Zhao, Yongbiao Chen, Zongwu Wang, Zhezhi He, Rui Yang, Qidong Tang, Tao Yang, Cheng Zhuo, Li Jiang. 1087-1092 [doi]
- YOLoC: deploy large-scale neural network by ROM-based computing-in-memory using residual branch on a chipYiming Chen, Guodong Yin, Zhanhong Tan, Mingyen Lee, Zekun Yang, Yongpan Liu, Huazhong Yang, Kaisheng Ma, Xueqing Li. 1093-1098 [doi]
- ASTERS: adaptable threshold spike-timing neuromorphic design with twin-column ReRAM synapsesZiru Li, Qilin Zheng, Bonan Yan, Ru Huang, Bing Li, Yiran Chen 0001. 1099-1104 [doi]
- SATO: spiking neural network acceleration via temporal-oriented dataflow and architectureFangxin Liu, Wenbo Zhao, Zongwu Wang, Yongbiao Chen, Tao Yang, Zhezhi He, Xiaokang Yang, Li Jiang. 1105-1110 [doi]
- LeHDC: learning-based hyperdimensional computing classifierShijin Duan, Yejia Liu, Shaolei Ren, Xiaolin Xu. 1111-1116 [doi]
- GENERIC: highly efficient learning engine on edge using hyperdimensional computingBehnam Khaleghi, Jaeyoung Kang 0001, Hanyang Xu, Justin Morris, Tajana Rosing. 1117-1122 [doi]
- Solving traveling salesman problems via a parallel fully connected ising machineQichao Tao, Jie Han 0001. 1123-1128 [doi]
- PATH: evaluation of boolean logic using path-based in-memory computingSven Thijssen, Sumit Kumar Jha 0001, Rickard Ewetz. 1129-1134 [doi]
- A length adaptive algorithm-hardware co-design of transformer on FPGA through sparse attention and dynamic pipeliningHongwu Peng, Shaoyi Huang, Shiyang Chen, Bingbing Li, Tong Geng, Ang Li, Weiwen Jiang, Wujie Wen, Jinbo Bi, Hang Liu, Caiwen Ding. 1135-1140 [doi]
- HDPG: hyperdimensional policy-based reinforcement learning for continuous controlYang Ni, Mariam Issa, Danny Abraham, Mahdi Imani, Xunzhao Yin, Mohsen Imani. 1141-1146 [doi]
- CarM: hierarchical episodic memory for continual learningSoobee Lee, Minindu Weerakoon, Jonghyun Choi, Minjia Zhang, Di Wang 0003, Myeongjae Jeon. 1147-1152 [doi]
- Shfl-BW: accelerating deep neural network inference with tensor-core aware weight pruningGuyue Huang, Haoran Li, Minghai Qin, Fei Sun, Yufei Ding, Yuan Xie. 1153-1158 [doi]
- QuiltNet: efficient deep learning inference on multi-chip accelerators using model partitioningJongho Park, Hyukjun Kwon, Seowoo Kim, Junyoung Lee, Minho Ha, Euicheol Lim, Mohsen Imani, Yeseong Kim. 1159-1164 [doi]
- Glimpse: mathematical embedding of hardware specification for neural compilationByung Hoon Ahn, Sean Kinzer, Hadi Esmaeilzadeh. 1165-1170 [doi]
- Bringing source-level debugging frameworks to hardware generatorsKeyi Zhang, Zain Asgar, Mark Horowitz. 1171-1176 [doi]
- Verifying SystemC TLM peripherals using modern C++ symbolic execution toolsPascal Pieper, Vladimir Herdt, Daniel Große, Rolf Drechsler. 1177-1182 [doi]
- Formal verification of modular multipliers using symbolic computer algebra and boolean satisfiabilityAlireza Mahzoon, Daniel Große, Christoph Scholl 0001, Alexander Konrad, Rolf Drechsler. 1183-1188 [doi]
- Silicon validation of LUT-based logic-locked IP coresGaurav Kolhe, Tyler Sheaves, Kevin Immanuel Gubbi, Tejas Kadale, Setareh Rafatirad, Sai Manoj PD, Avesta Sasan, Hamid Mahmoodi, Houman Homayoun. 1189-1194 [doi]
- Efficient bayesian yield analysis and optimization with active learningShuo Yin, Xiang Jin, Linxu Shi, Kang Wang, Wei W. Xing. 1195-1200 [doi]
- Accelerated synthesis of neural network-based barrier certificates using collaborative learningJun Xia, Ming Hu 0003, Xin Chen, Mingsong Chen. 1201-1206 [doi]
- A timing engine inspired graph neural network model for pre-routing slack predictionZizheng Guo, Mingjie Liu, Jiaqi Gu, Shuhan Zhang, David Z. Pan, Yibo Lin. 1207-1212 [doi]
- Accurate timing prediction at placement stage with look-ahead RC networkXu He, Zhiyong Fu, Yao Wang 0002, Chang Liu, Yang Guo. 1213-1218 [doi]
- Timing macro modeling with graph neural networksKevin Kai-Chun Chang, Chun-Yao Chiang, Pei-Yu Lee, Iris Hui-Ru Jiang. 1219-1224 [doi]
- Worst-case dynamic power distribution network noise prediction using convolutional neural networkXiao Dong, Yufei Chen, Xunzhao Yin, Cheng Zhuo. 1225-1230 [doi]
- GATSPI: GPU accelerated gate-level simulation for power improvementYanqing Zhang, Haoxing Ren, Akshay Sridharan, Brucek Khailany. 1231-1236 [doi]
- PPATuner: pareto-driven tool parameter auto-tuning in physical design via gaussian process transfer learningHao Geng, Qi Xu, Tsung-Yi Ho, Bei Yu. 1237-1242 [doi]
- Efficient maximum data age analysis for cause-effect chains in automotive systemsRan Bi, Xinbin Liu, Jiankang Ren, Pengfei Wang, Huawei Lv, Guozhen Tan. 1243-1248 [doi]
- Optimizing parallel PREM compilation over nested loop structuresZhao Gu, Rodolfo Pellizzoni. 1249-1254 [doi]
- Scheduling and analysis of real-time tasks with parallel critical sectionsYang Wang 0082, Xu Jiang 0004, Nan Guan, Mingsong Lv, Dong Ji, Wang Yi 0001. 1255-1260 [doi]
- BlueScale: a scalable memory architecture for predictable real-time computing on highly integrated SoCsZhe Jiang 0004, Kecheng Yang 0001, Neil C. Audsley, Nathan Fisher, Weisong Shi, Zheng Dong 0002. 1261-1266 [doi]
- Precise and scalable shared cache contention analysis for WCET estimationWei Zhang 0173, Mingsong Lv, Wanli Chang, Lei Ju. 1267-1272 [doi]
- Predictable sharing of last-level cache partitions for multi-core safety-critical systemsZhuanhao Wu, Hiren D. Patel. 1273-1278 [doi]
- Thermal-aware optical-electrical routing codesign for on-chip signal communicationsYu-Sheng Lu, Kuan-Cheng Chen, Yu-Ling Hsu, Yao-Wen Chang. 1279-1284 [doi]
- Power-aware pruning for ultrafast, energy-efficient, and accurate optical neural network designNaoki Hattori, Yutaka Masuda, Tohru Ishihara, Akihiko Shinya, Masaya Notomi. 1285-1290 [doi]
- REACT: a heterogeneous reconfigurable neural network accelerator with software-configurable NoCs for training and inference on wearablesMohit Upadhyay, Rohan Juneja, Bo Wang 0020, Jun Zhou 0014, Weng-Fai Wong, Li-Shiuan Peh. 1291-1296 [doi]
- LHNN: lattice hypergraph neural network for VLSI congestion predictionBowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng. 1297-1302 [doi]
- Floorplanning with graph attentionYiting Liu, Ziyi Ju, Zhengming Li, Mingzhi Dong, Hai Zhou, Jia Wang, Fan Yang, Xuan Zeng 0001, Li Shang. 1303-1308 [doi]
- Xplace: an extremely fast and extensible global placement frameworkLixin Liu, Bangqi Fu, Martin D. F. Wong, Evangeline F. Y. Young. 1309-1314 [doi]
- Differentiable-timing-driven global placementZizheng Guo, Yibo Lin. 1315-1320 [doi]
- TAAS: a timing-aware analytical strategy for AQFP-capable placement automationPeiyan Dong, Yanyue Xie, Hongjia Li, Mengshu Sun, Olivia Chen, Nobuyuki Yoshikawa, Yanzhi Wang. 1321-1326 [doi]
- A cross-layer approach to cognitive computing: invitedGobinda Saha, Cheng Wang, Anand Raghunathan, Kaushik Roy 0001. 1327-1330 [doi]
- Generative self-supervised learning for gate sizing: invitedSiddhartha Nath, Geraldo Pradipta, Corey Hu, Tian Yang, Brucek Khailany, Haoxing Ren. 1331-1334 [doi]
- Hammer: a modular and reusable physical design flow tool: invitedHarrison Liew, Daniel Grubb, John Wright, Colin Schmidt 0001, Nayiri Krzysztofowicz, Adam M. Izraelevitz, Edward Wang, Krste Asanovic, Jonathan Bachrach, Borivoje Nikolic. 1335-1338 [doi]
- mflowgen: a modular flow generator and ecosystem for community-driven physical design: invitedAlex Carsello, James J. Thomas, Ankita Nayak, Po-Han Chen, Mark Horowitz, Priyanka Raina, Christopher Torng. 1339-1342 [doi]
- A distributed approach to silicon compilation: invitedAndreas Olofsson, William Ransohoff, Noah Moroze. 1343-1346 [doi]
- Improving GNN-based accelerator design automation with meta learningYunsheng Bai, Atefeh Sohrabizadeh, Yizhou Sun, Jason Cong. 1347-1350 [doi]
- Accelerator design with decoupled hardware customizations: benefits and challenges: invitedDebjit Pal, Yi-Hsiang Lai, Shaojie Xiang, Niansong Zhang, Hongzheng Chen, Jeremy Casas, Pasquale Cocchini, Zhenkun Yang, Jin Yang, Louis-Noël Pouchet, Zhiru Zhang. 1351-1354 [doi]
- ScaleHLS: a scalable high-level synthesis framework with multi-level transformations and optimizations: invitedHanchen Ye, HyeGang Jun, Hyunmin Jeong, Stephen Neuendorffer, Deming Chen. 1355-1358 [doi]
- The SODA approach: leveraging high-level synthesis for hardware/software co-design and hardware specialization: invitedNicolas Bohm Agostini, Serena Curzel, Ankur Limaye, Vinay Amatya, Marco Minutoli, Vito Giovanni Castellana, Joseph B. Manzano, Antonino Tumeo, Fabrizio Ferrandi. 1359-1362 [doi]
- Automatic oracle generation in microsoft's quantum development kit using QIR and LLVM passesMathias Soeken, Mariia Mykhailova. 1363-1366 [doi]
- The basis of design tools for quantum computing: arrays, decision diagrams, tensor networks, and ZX-calculusRobert Wille, Lukas Burgholzer, Stefan Hillmich, Thomas Grurl, Alexander Ploier, Tom Peham. 1367-1370 [doi]
- Secure by construction: addressing security vulnerabilities introduced during high-level synthesis: invitedMd Rafid Muttaki, Zahin Ibnat, Farimah Farahmandi. 1371-1374 [doi]
- High-level design methods for hardware security: is it the right choice? invitedChristian Pilato, Donatella Sciuto, Benjamin Tan 0001, Siddharth Garg, Ramesh Karri. 1375-1378 [doi]
- Trusting the trust anchor: towards detecting cross-layer vulnerabilities with hardware fuzzingChen Chen, Rahul Kande, Pouya Mahmoody, Ahmad-Reza Sadeghi, J. V. Rajendran. 1379-1383 [doi]
- Automating hardware security property generation: invitedRyan Kastner, Francesco Restuccia, Andres Meza, Sayak Ray, Jason M. Fung, Cynthia Sturton. 1384-1387 [doi]
- Efficient timing propagation with simultaneous structural and pipeline parallelisms: late breaking resultsCheng-Hsiang Chiu, Tsung-Wei Huang. 1388-1389 [doi]
- A fast and low-cost comparison-free sorting engine with unary computing: late breaking resultsAmir Hossein Jalilvand, Seyedeh Newsha Estiri, Samaneh Naderi, M. Hassan Najafi, Mohsen Imani. 1390-1391 [doi]
- Flexible chip placement via reinforcement learning: late breaking resultsFu-Chieh Chang 0001, Yu-Wei Tseng, Ya-Wen Yu, Ssu-Rui Lee, Alexandru Cioba, I-Lun Tseng, Da-shan Shiu, Jhih-Wei Hsu, Cheng-Yuan Wang, Chien-Yi Yang, Ren-Chu Wang, Yao-Wen Chang, Tai-Chen Chen, Tung-Chieh Chen. 1392-1393 [doi]
- FPGA-aware automatic acceleration framework for vision transformer with mixed-scheme quantization: late breaking resultsMengshu Sun, Zhengang Li, Alec Lu, Haoyu Ma, Geng Yuan, Yanyue Xie, Hao Tang, Yanyu Li, Miriam Leeser, Zhangyang Wang, Xue Lin, Zhenman Fang. 1394-1395 [doi]
- Hardware-efficient stochastic rounding unit design for DNN training: late breaking resultsSung-En Chang, Geng Yuan, Alec Lu, Mengshu Sun, Yanyu Li, Xiaolong Ma, Zhengang Li, Yanyue Xie, Minghai Qin, Xue Lin, Zhenman Fang, Yanzhi Wang. 1396-1397 [doi]
- Placement initialization via a projected eigenvector algorithm: late breaking resultsPengwen Chen, Chung-Kuan Cheng, Albert Chern, Chester Holtz, Aoxi Li, Yucheng Wang. 1398-1399 [doi]
- Subgraph matching based reference placement for PCB designs: late breaking resultsMiaodi Su, Yifeng Xiao, Shu Zhang, Haiyuan Su, Jiacen Xu, Huan He, Ziran Zhu, Jianli Chen, Yao-Wen Chang. 1400-1401 [doi]
- Thermal-aware drone battery management: late breaking resultsHojun Choi, Youngmoon Lee. 1402-1403 [doi]
- Waveform-based performance analysis of RISC-V processors: late breaking resultsLucas Klemmer, Daniel Große. 1404-1405 [doi]