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Payam Heydari. Design issues in low-voltage high-speed current-mode logic buffers. In Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003. pages 21-26, ACM, 2003. [doi]
Possibly Related PublicationsThe following publications are possibly variants of this publication: Design and Analysis of Low-Voltage Current-Mode Logic BuffersPayam Heydari. isqed 2003: 293-298 [doi] Design of ultrahigh-speed low-voltage CMOS CML buffers and latchesPayam Heydari, Ravindran Mohanavelu. tvlsi, 12(10):1081-1093, 2004. [doi]
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